# US 12,224,201 B2 · Single crystalline silicon stack formation and bonding to a cmos wafer

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- Number: US 12,224,201 B2
- Document ID: US12224201B2
- Status: Granted
- Kind: B2
- Application number: 18/403,866
- Filed: 2024-01-04
- Published: 2024-05-09
- Granted: 2025-02-11
- Earliest claimed: 2020-11-02
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Si-Woo Lee; Byung Yoon Kim
- Web page: https://patentgrep.com/patent/US12224201B2

## CPC

- H10P 90/1914: {using bonding}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3252: {Alternating layers, e.g. superlattice}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3458: {Monocrystalline}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 90/00: Package configurations
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complementary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.

## Claims

### Claim 1

A method, comprising:
forming a layer of single crystal silicon germanium onto a surface of a silicon substrate;
epitaxially growing the silicon germanium to form a thicker single crystal silicon germanium layer;
forming a layer of single crystal silicon onto a surface of the thicker single crystal silicon germanium layer;
epitaxially growing the single crystal silicon to form a thicker single crystal silicon layer; and
forming, in repeating iterations, a number of additional layers of single crystal silicon germanium and single crystal silicon to form a vertical stack of alternating single crystal silicon and single crystal silicon germanium layers.

### Claim 2 (depends on 1)

The method of claim 1, further comprising, processing the vertical stack to expose a first surface of a first layer of single crystal silicon germanium and a first surface of a second layer of single crystal silicon germanium.

### Claim 3 (depends on 2)

The method of claim 2, further comprising, forming a hard mask material on the first surface of the first layer of single crystal silicon germanium.

### Claim 4 (depends on 3)

The method of claim 3, further comprising, forming a bonding material on the first surface of the second layer of single crystal silicon germanium.

### Claim 5 (depends on 4)

The method of claim 4, further comprising, bonding the bonding material to a surface of a different substrate having a number of CMOS components formed thereon.

### Claim 6 (depends on 5)

The method of claim 5, wherein the different substrate has a bonding material formed on a surface thereof, and wherein the method further comprises bonding the bonding material formed on the surface of the different substrate to the bonding material formed on the first surface of the second layer of single crystal silicon germanium.

### Claim 7 (depends on 1)

The method of claim 1, further comprising, bonding the vertical stack to a different substrate having CMOS components formed thereon, the different substrate being processed separately from the substrate on which the vertical stack is formed.

### Claim 8 (depends on 1)

The method of claim 1, further comprising forming vertical dynamic random access memory (DRAM) cells in the vertical stack.

### Claim 9 (depends on 8)

The method of claim 8, further comprising forming access devices of the DRAM cells to have single crystal silicon channels.

### Claim 10

A method, comprising:
forming a first layer of single crystal silicon germanium onto a surface of a first substrate;
forming a first layer of single crystal silicon onto a surface of the single crystal silicon germanium;
forming, in repeating iterations, a number of additional layers of single crystal silicon germanium and single crystal silicon to form a vertical stack of alternating single crystal silicon and single crystal silicon germanium layers; and
bonding a surface of the vertical stack to a second substrate.

### Claim 11 (depends on 10)

The method of claim 10, wherein the second substrate comprises a number of CMOS components formed thereon, and wherein the method further comprises:
bonding the first substrate to the second substrate subsequent to forming the vertical stack.

### Claim 12 (depends on 11)

The method of claim 11, wherein the temperature range used for the formation of the vertical stack is 600 degree Celsius (° C.) to 1100° C.

### Claim 13 (depends on 11)

The method of claim 11, wherein the first layer of single crystal silicon germanium serves as a seed layer, and wherein the method includes heating the first layer of single crystal silicon germanium to increase a thickness of the first layer of single crystal silicon germanium via epitaxial growth.

### Claim 14 (depends on 13)

The method of claim 13, wherein the seed layer has a thickness of about 100 Angstroms.

### Claim 15 (depends on 14)

The method of claim 14, wherein the thickness of the first layer of single crystal silicon germanium is about 1,000 Angstroms after the epitaxial growth.

### Claim 16 (depends on 11)

The method of claim 11, wherein the first layer of single crystal silicon serves as a seed layer, and wherein the method includes heating the first layer of single crystal silicon to increase a thickness of the first layer of single crystal silicon via epitaxial growth.

### Claim 17 (depends on 16)

The method of claim 16, wherein the seed layer has a thickness of about 50 Angstroms.

### Claim 18 (depends on 17)

The method of claim 17, wherein the thickness of the first layer of single crystal silicon is about 300 Angstroms after the epitaxial growth.

### Claim 19

A method, comprising:
forming a vertical stack of repeating iterations of single crystal silicon germanium and single crystal silicon layers on a substrate, wherein the vertical stack includes at least two iterations, and wherein forming each iteration comprises:
forming a seed layer of single crystal silicon germanium;
epitaxially growing single crystal silicon germanium from the seed layer of crystal silicon germanium to a desired first thickness;
forming a seed layer of single crystal silicon onto a surface of the epitaxially grown single crystal silicon germanium; and
epitaxially growing single crystal silicon from the seed layer of single crystal silicon to a desired second thickness; and
forming dynamic random access memory cells in the vertical stack.

### Claim 20 (depends on 19)

The method of claim 19, wherein the method includes bonding the substrate to a different substrate prior to forming the memory cells in the vertical stack.