# US 12,224,183 B2 · Method of manufacturing semiconductor device

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- Number: US 12,224,183 B2
- Document ID: US12224183B2
- Status: Granted
- Kind: B2
- Application number: 17/896,171
- Filed: 2022-08-26
- Published: 2023-05-04
- Granted: 2025-02-11
- Earliest claimed: 2022-08-26
- Assignees: Chipbond Technology Corporation
- Applicants: Chipbond Technology Corporation
- Inventors: Shrane-Ning Jenq; Wen-Cheng Hsu; Chen-Yu Wang; Chih-Ming Kuo; Chwan-Tyaw Chen; Lung-Hua Ho
- Web page: https://patentgrep.com/patent/US12224183B2

## CPC

- C23C 28/023: {only coatings of metal elements only}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- C23C 18/1653: {Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating}
- C23C 18/54: Contact plating, i.e. electroless electrochemical plating
- C23C 28/02: only coatings {only including layers} of metallic material
- C25D 7/123: {Semiconductors first coated with a seed layer or a conductive layer}
- H10P 14/40: of conductive or resistive materials
- H10P 50/267: {using plasmas}
- H10P 50/287: {by chemical means}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/66: Conductive materials thereof
- H10W 72/50: Bond wires
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- C25D: PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A package including a first carrier, a seed layer, wires, a die and a molding material is provided. The first carrier is removed to expose the seed layer after disposing a second carrier on the molding material, then the seed layer is removed to expose the wires, and a gold layer is deposited on each of the wires by immersion gold plating, finally a semiconductor device is obtained. The gold layer is provided to protect the wires from oxidation and improve solder joint reliability.

## Claims

### Claim 1

A method of manufacturing semiconductor device comprising the steps of:
providing a package including a first carrier, a seed layer, a plurality of wires, a die and a molding material, the seed layer is formed on the first carrier, the plurality of wires are formed on the seed layer, the die is bonded to the plurality of wires, and the die and the plurality of wires are covered by the molding material;
disposing a second carrier on the molding material;
removing the first carrier to expose the seed layer;
removing the seed layer to expose the plurality of wires; and
depositing a gold layer on each of the plurality of wires by immersion gold plating.

### Claim 2 (depends on 1)

The method of manufacturing semiconductor device in accordance with claim 1, wherein each of the plurality of wires includes a nickel layer and a copper layer, the nickel layer is formed on the seed layer by pure nickel electroplating, the copper layer is formed on the nickel layer, the nickel layer is exposed after removing the seed layer, and the gold layer is deposited on the nickel layer by immersion gold plating.

### Claim 3 (depends on 2)

The method of manufacturing semiconductor device in accordance with claim 2, wherein the copper layer is a redistribution layer.

### Claim 4 (depends on 1)

The method of manufacturing semiconductor device in accordance with claim 1, wherein each of the plurality of wires includes a copper layer which is formed on the seed layer, the copper layer is exposed after removing the seed layer, and the gold layer is deposited on the copper layer by immersion gold plating.

### Claim 5 (depends on 4)

The method of manufacturing semiconductor device in accordance with claim 4, wherein the copper layer is a redistribution layer.

### Claim 6 (depends on 1)

The method of manufacturing semiconductor device in accordance with claim 1, wherein the seed layer is removed by plasma etching.

### Claim 7 (depends on 1)

The method of manufacturing semiconductor device in accordance with claim 1, wherein the plurality of wires are formed on the seed layer using a patterned dielectric layer, and a top surface and a lateral surface of each of the plurality of wires are exposed after removing the seed layer and a top part of the patterned dielectric layer by plasma etching.

### Claim 8 (depends on 7)

The method of manufacturing semiconductor device in accordance with claim 7, wherein the gold layer is deposited on the top surface and the lateral surface of each of the plurality of wires.

### Claim 9 (depends on 7)

The method of manufacturing semiconductor device in accordance with claim 7, wherein a removed thickness of the patterned dielectric layer is less than or equal to 1.5 μm.

### Claim 10 (depends on 1)

The method of manufacturing semiconductor device in accordance with claim 1, wherein the plurality of wires are formed on the seed layer using a patterned dielectric layer, each of the plurality of wires includes a nickel layer and a copper layer, the nickel layer is formed on the seed layer by pure nickel electroplating, the copper layer is formed on the nickel layer, a top surface and a lateral surface of the nickel layer are exposed after removing the seed layer and a top part of the pattern dielectric layer by plasma etching.

### Claim 11 (depends on 10)

The method of manufacturing semiconductor device in accordance with claim 10, wherein the gold layer is deposited on the top surface and the lateral surface of the nickel layer.

### Claim 12 (depends on 10)

The method of manufacturing semiconductor device in accordance with claim 10, wherein a removed thickness of the patterned dielectric layer is less than or equal to 1.5 μm.

### Claim 13 (depends on 1)

The method of manufacturing semiconductor device in accordance with claim 1, wherein the plurality of wires are formed on the seed layer using a patterned dielectric layer, each of the plurality of wires includes a copper layer which is formed on the seed layer, a top surface and a lateral surface of the copper layer are exposed after removing the seed layer and a top part of the patterned dielectric layer by plasma etching.

### Claim 14 (depends on 13)

The method of manufacturing semiconductor device in accordance with claim 13, wherein the gold layer is deposited on the top surface and the lateral surface of the copper layer.

### Claim 15 (depends on 13)

The method of manufacturing semiconductor device in accordance with claim 13, wherein a removed thickness of the patterned dielectric layer is less than or equal to 1.5 μm.

### Claim 16 (depends on 1)

The method of manufacturing semiconductor device in accordance with claim 1, wherein the first carrier includes a substrate and a release layer which is located on the substrate, the seed layer is formed on the release layer and exposed after removing the substrate and the release layer.

### Claim 17 (depends on 1)

The method of manufacturing semiconductor device in accordance with claim 1, wherein the seed layer is a titanium-tungsten/copper layer or a titanium/copper layer.

### Claim 18 (depends on 1)

The method of manufacturing semiconductor device in accordance with claim 1, wherein a solder ball is formed on the gold layer after depositing the gold layer.