# US 12,224,179 B2 · Metal heterojunction structure with capping metal layer

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- Number: US 12,224,179 B2
- Document ID: US12224179B2
- Status: Granted
- Kind: B2
- Application number: 18/184,438
- Filed: 2023-03-15
- Published: 2023-07-20
- Granted: 2025-02-11
- Earliest claimed: 2018-09-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yi-Sheng Lin; Chi-Jen Liu; Chi-Hsiang Shen; Te-Ming Kung; Chun-Wei Hsu; Chia-Wei Ho; Yang-Chun Cheng; William Weilun Hong; Liang-Guang Chen; Kei-Wei Chen
- Web page: https://patentgrep.com/patent/US12224179B2

## CPC

- H10P 52/403: {of conductive or resistive materials}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/0698: {Local interconnections}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/095: {by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096)}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/4421: {the principal metal being copper}
- H10W 20/4437: {the principal metal being a transition metal}
- H10W 20/4441: {the principal metal being a refractory metal}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- C09G 1/02: containing abrasives or grinding agents {(abrasives as such C09K3/14; polishing of semi-conductors H10P52/40)}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- C09G: POLISHING COMPOSITIONS (French polish C09F11/00); SKI WAXES

## Abstract

The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

## Claims

### Claim 1

A structure, comprising:
a first dielectric layer, the first dielectric layer being a monolithic layer;
a first metal structure within the first dielectric layer, an upper surface of the first metal structure being lower than an upper surface of the first dielectric layer;
a second metal structure over the upper surface of the first metal structure;
wherein an upper portion of the first dielectric layer includes a doping property that is different from a lower portion of the first dielectric layer.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the doping property of the upper portion of the first dielectric layer introduces a tensile stress in the upper portion of the first dielectric layer against the second metal structure.

### Claim 3 (depends on 1)

The structure of claim 1, wherein the upper portion of the first dielectric layer include ions of one or more of germanium, silicon, carbon, nitrogen, phosphorus or boron.

### Claim 4 (depends on 1)

The structure of claim 1, further comprising:
a third metal structure directly over the second metal structure; and
a second dielectric layer that surrounds the third metal structure.

### Claim 5 (depends on 4)

The structure of claim 4, wherein a gap between the first dielectric layer and the second metal structure does not allow a chemical solution used in an CMP procedure to pass through the gap.

### Claim 6 (depends on 1)

The structure of claim 1, wherein an upper surface of the second metal structure is coplanar with an upper surface of the first dielectric layer.

### Claim 7 (depends on 4)

The structure of claim 4, wherein the second metal structure and the third metal structure are conductive vias.

### Claim 8 (depends on 1)

The structure of claim 1, wherein the second metal structure and the first metal structure include different conductive materials from one another.

### Claim 9 (depends on 8)

The structure of claim 8, wherein a conductive material of the first metal structure is different from a conductive material of the second metal structure in reacting to at least one of an acidic solution or an alkaline solution.

### Claim 10 (depends on 8)

The structure of claim 8, wherein one of the first metal structure or the second metal structure is tungsten and another one of the first metal structure or the second metal structure is one or more of cobalt or copper.

### Claim 11 (depends on 1)

The structure of claim 1, wherein the second metal structure extends laterally beyond the first metal structure at least in one direction.

### Claim 12 (depends on 1)

The structure of claim 1, wherein the first metal structure includes a different diameter than the second metal structure.

### Claim 13 (depends on 1)

The structure of claim 1, wherein the second metal structure partially misaligns with the first metal structure.

### Claim 14

A semiconductor structure, comprising:
a substrate;
a dielectric layer over the substrate, the dielectric layer being a monolithic layer and including an upper portion and a lower portion that is closer to the substrate than the upper portion;
a conductive via structure within the dielectric layer, an upper surface of the conductive via structure being lower than an upper surface of the dielectric layer adjacent to the conductive via structure; and
a conductive cap structure directly over the conductive via structure, an upper surface of the conductive cap structure being one of substantially at a same level with or higher than the upper surface of the dielectric layer adjacent to the conductive via structure, the conductive cap structure laterally interfacing with the upper portion of the dielectric layer,
wherein the upper portion of the dielectric layer has a strain force again an interface between the upper portion of the dielectric layer and the conductive cap structure.

### Claim 15 (depends on 14)

The semiconductor structure of claim 14, wherein the conductive cap structure extends laterally beyond the conductive via structure at least in one direction.

### Claim 16 (depends on 14)

The semiconductor structure of claim 14, wherein the conductive cap structure partially misaligns with the conductive via structure.

### Claim 17 (depends on 14)

The semiconductor structure of claim 14, wherein the upper portion of the dielectric layer includes a tensile stress.

### Claim 18 (depends on 14)

The semiconductor structure of claim 14, wherein the upper portion of the dielectric layer includes a doping characteristic that is different from that of the lower portion of the dielectric layer.

### Claim 19

A structure, comprising:
a substrate;
a first dielectric layer over the substrate, the dielectric layer being a monolithic layer and including an upper portion and a lower portion that is closer to the substrate than the upper portion;
a first metal structure within the first dielectric layer, an upper surface of the first metal structure being lower than an upper surface of the first dielectric layer that is adjacent to the upper surface of the first metal structure; and
a second metal structure over the upper surface of the first metal structure, the second metal structure adjacent to the upper portion of the first dielectric layer;
wherein the upper portion of the first dielectric layer is doped to include an expansion force.

### Claim 20 (depends on 6)

The structure of claim 6, wherein the upper portion of the first dielectric layer includes implanted ions of one or more of germanium, silicon, carbon, nitrogen, phosphorus or boron.