# US 12,224,173 B2 · Polycrystalline ceramic substrate and method of manufacture

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- Number: US 12,224,173 B2
- Document ID: US12224173B2
- Status: Granted
- Kind: B2
- Application number: 17/518,894
- Filed: 2021-11-04
- Published: 2022-02-24
- Granted: 2025-02-11
- Earliest claimed: 2016-06-24
- Assignees: QROMIS, Inc.
- Applicants: Qromis, Inc.
- Inventors: Vladimir Odnoblyudov; Cem Basceri; Shari Farrens
- Web page: https://patentgrep.com/patent/US12224173B2

## CPC

- H10P 14/2921: {being crystalline insulating materials}
- H10P 90/1914: {using bonding}
- C23C 16/401: {containing silicon}
- C23C 16/50: using electric discharges {(generation and control of plasma in discharge tubes for surface treatment H01J37/32, H01J37/34)}
- C23C 16/56: After-treatment
- C30B 29/06: Silicon
- C30B 29/406: {Gallium nitride}
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D 86/01: Manufacture or treatment
- H10H 20/0137: {the light-emitting regions comprising nitride materials}
- H10H 20/81: Bodies
- H10H 20/815: having stress relaxation structures, e.g. buffer layers
- H10H 20/819: characterised by their shape, e.g. curved or truncated substrates
- H10P 14/2925: {Surface structures}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3258: {Crystal orientation}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3416: {Nitrides}
- H10P 90/00: Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- C30B 29/403: {AIII-nitrides}
- H10H 20/018: {Bonding of wafers}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- C30B: SINGLE-CRYSTAL GROWTH (by using ultra-high pressure, e.g. for the formation of diamonds, B01J3/06); UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL (zone-refining of metals or alloys C22B); PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE (casting of metals, casting of other substances by the same processes or devices B22D; working of plastics B29; modifying the physical structure of metals or alloys C21D, C22F); SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE (for producing semiconductor devices or parts thereof H10); APPARATUS THEREFOR
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS

## Abstract

An engineered substrate structure includes a ceramic substrate having a front surface characterized by a plurality of peaks. The ceramic substrate includes a polycrystalline material. The engineered substrate structure also includes a planarization layer comprising a planarization layer material and coupled to the front surface of the ceramic substrate. The planarization layer defines fill regions filled with the planarization layer material between adjacent peaks of the plurality of peaks on the front surface of the ceramic substrate. The engineered substrate structure further includes a barrier shell encapsulating the ceramic substrate and the planarization layer, wherein the barrier shell has a front side and a back side, a bonding layer coupled to the front side of the barrier shell, a single crystal layer coupled to the bonding layer, and a conductive layer coupled to the back side of the barrier shell.

## Claims

### Claim 1

An engineered substrate structure comprising:
a ceramic substrate having a front surface characterized by a plurality of peaks, the ceramic substrate comprising a polycrystalline material;
a planarization layer comprising a planarization layer material and coupled to the front surface of the ceramic substrate, the planarization layer defining fill regions filled with the planarization layer material between adjacent peaks of the plurality of peaks on the front surface of the ceramic substrate;
a barrier shell encapsulating the ceramic substrate and the planarization layer, wherein the barrier shell has a front side and a back side;
a bonding layer coupled to the front side of the barrier shell;
a single crystal layer coupled to the bonding layer; and
an electrically conductive layer coupled to the back side of the barrier shell.

### Claim 2 (depends on 1)

The engineered substrate structure of claim 1 further comprising an adhesion promotion layer disposed between the front surface of the ceramic substrate and the planarization layer.

### Claim 3 (depends on 1)

The engineered substrate structure of claim 1 wherein the ceramic substrate comprises polycrystalline aluminum nitride.

### Claim 4 (depends on 1)

The engineered substrate structure of claim 1 wherein the ceramic substrate comprises polycrystalline silicon carbide.

### Claim 5 (depends on 1)

The engineered substrate structure of claim 1 wherein the single crystal layer comprises single crystal silicon.

### Claim 6 (depends on 5)

The engineered substrate structure of claim 5 further comprising an epitaxial silicon layer coupled to the single crystal silicon.

### Claim 7 (depends on 1)

The engineered substrate structure of claim 1 further comprising a thermally conductive layer coupled to at least a portion of the barrier shell.

### Claim 8 (depends on 1)

The engineered substrate structure of claim 1 wherein the electrically conductive layer comprises polysilicon.

### Claim 9 (depends on 1)

The engineered substrate structure of claim 1 further comprising a second bonding layer disposed between the bonding layer and the single crystal layer.

### Claim 10 (depends on 9)

The engineered substrate structure of claim 9 wherein the front surface of the ceramic substrate is characterized by a root mean square (RMS) roughness in a range of 50-600 nm, and the second bonding layer is characterized by an RMS roughness in a range of 0.5-5 nm.

### Claim 11 (depends on 9)

The engineered substrate structure of claim 9 wherein the bonding layer comprises silicon oxide and the second bonding layer comprises silicon oxide.

### Claim 12 (depends on 11)

The engineered substrate structure of claim 11 wherein the second bonding layer has a thickness between 100 nm and 1,000 nm.

### Claim 13 (depends on 9)

The engineered substrate structure of claim 9 wherein the second bonding layer comprises a different material than the bonding layer.

### Claim 14 (depends on 13)

The engineered substrate structure of claim 13 wherein the bonding layer comprises silicon oxide and the second bonding layer comprises diamond-like carbon (DLC).

### Claim 15 (depends on 1)

The engineered substrate structure of claim 1 wherein the ceramic substrate comprises polycrystalline aluminum nitride and the barrier shell comprises silicon nitride.

### Claim 16 (depends on 1)

The engineered substrate structure of claim 1 wherein the single crystal layer comprises single crystal Ga2O3.

### Claim 17 (depends on 1)

The engineered substrate structure of claim 1 wherein the single crystal layer comprises single crystal SiC.

### Claim 18 (depends on 1)

The engineered substrate structure of claim 1 wherein the single crystal layer comprises single crystal GaN.

### Claim 19 (depends on 1)

The engineered substrate structure of claim 1 wherein the single crystal layer comprises single crystal sapphire.