# US 12,224,037 B2 · Apparatuses and methods of memory access control with section predecoding and section selection > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,037 B2 - Document ID: US12224037B2 - Status: Granted - Kind: B2 - Application number: 17/840,461 - Filed: 2022-06-14 - Published: 2023-12-14 - Granted: 2025-02-11 - Earliest claimed: 2022-06-14 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Manami Senoo; Hidekazu Noguchi; Yoshio Mizukane - Web page: https://patentgrep.com/patent/US12224037B2 ## CPC - G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers} - G11C 8/10: Decoders - G11C 7/08: Control thereof - G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals} - G11C 7/109: {Control signal input circuits} - G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 29/76: {using address translation or modifications} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Apparatuses and methods for controlling access to memory cell matrices are described. An example apparatus includes: a plurality of memory cell matrices including memory cells, a plurality of sections wherein each section is included in a memory cell matrix of the plurality of memory cell matrices; a section predecoder that activates one section signal among a plurality of corresponding section signals responsive to a portion of row address signals; a section selection control circuit that provides a set of first section sub signals including an active first section sub signal and a set of second section sub signals including an active second section sub signal based on the plurality of section signals; and a plurality of section selection circuits corresponding to the plurality of sections. One section selection circuit among the plurality of section selection circuits activates the corresponding section responsive to the active first and second section sub signals. ## Claims ### Claim 1 An apparatus comprising: a plurality of memory cell matrices including memory cells; a plurality of sections wherein each section is included in a memory cell matrix of the plurality of memory cell matrices; a section predecoder configured to decode a portion of row address signals and further configured to activate a section signal among a plurality of corresponding section signals responsive to the portion of row address signals; a section selection control circuit configured to provide a plurality of sets of section sub signals based on the plurality of section signals, the plurality of sets of section sub signals including: a set of first section sub signals including an active first section sub signal; and a set of second section sub signals including an active second section sub signal; and a plurality of section selection circuits corresponding to the plurality of sections, wherein one section selection circuit among the plurality of section selection circuits is configured to activate the corresponding section responsive to the active first and second section sub signals. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the set of first section sub signals including the active first section sub signal and the set of second section sub signals including the active second section sub signal is unique to the activated section signal. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein a number of signals in the plurality of section signals is less than a number of signals in the plurality of sets of section sub signals. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein a number of signals in the plurality of section signals is less than a number of sections expressed by the plurality of the first and second sets of section sub signals. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the plurality of memory cell matrices comprise a memory cell matrix at an end, and wherein a size of each section of the plurality of sections is the same as a size of the memory cell matrix. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the size of each section of the plurality of sections corresponds to a number of word lines coupled to each section. ### Claim 7 (depends on 5) The apparatus of claim 5, further comprising a sense amplifier between the memory cell matrix that is a first memory cell matrix and a second memory cell matrix adjacent to the first memory cell matrix, wherein the first memory cell matrix comprises folded bit lines that extend from the sense amplifier to the end and further extend from the end towards the sense amplifier. ### Claim 8 (depends on 5) The apparatus of claim 5, wherein the memory cell matrix at the end is a first memory cell matrix, wherein the plurality of memory cell matrices comprise a second memory cell matrix, and wherein the second memory cell matrix includes two or more sections among the plurality of sections. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the second memory cell matrix is disposed between two memory cell matrices of the plurality of memory cell matrices. ### Claim 10 (depends on 8) The apparatus of claim 8, wherein a number of word lines coupled to the second memory cell matrix is equal to or greater than twice a number of word lines coupled to the first memory cell matrix. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein: the portion of row address signals comprises a second portion of the row address signals; and the apparatus further comprises: a bank comprising a plurality of blocks, the plurality of blocks comprising the plurality of memory cell matrices; and a block decoder configured to decode a first portion of the row address signals different from the second portion of the row address signals, and further configured to provide one or more block signals that is configured to activate one of the plurality of blocks responsive to the first portion of row address signals. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein each block comprises a same number of sections and a same number of corresponding section selection circuits. ### Claim 13 An apparatus comprising: a plurality of memory cell matrices including memory cells; a plurality of sections wherein each section is included in a memory cell matrix of the plurality of memory cell matrices; a section predecoder configured to decode a portion of row address signals and further configured to activate a section signal among a plurality of corresponding section signals responsive to the portion of row address signals; a section selection control circuit configured to provide a plurality of sets of section sub signals based on the plurality of section signals, the plurality of sets of section sub signals including: a set of first section sub signals including an active first section sub signal; and a set of second section sub signals including an active second section sub signal; and a plurality of section selection circuits corresponding to the plurality of sections, wherein one section selection circuit among the plurality of section selection circuits is configured to activate the corresponding section responsive to the active first and second section sub signals, wherein: the plurality of memory cell matrices comprises a first memory cell matrix at an end; the plurality of memory cell matrices comprises a second memory cell matrix; and a number of word lines coupled to the second memory cell matrix is equal to or greater than twice a number of word lines coupled to the first memory cell matrix. ### Claim 14 (depends on 13) The apparatus of claim 13, further comprising a sense amplifier between the first memory cell matrix and a third memory cell matrix adjacent to the first memory cell matrix, wherein the first memory cell matrix comprises folded bit lines that extend from the sense amplifier to the end and further extend from the end towards the sense amplifier. ### Claim 15 (depends on 13) The apparatus of claim 13, wherein the set of first section sub signals including the active first section sub signal and the set of second section sub signals including the active second section sub signal is unique to the activated section signal. ### Claim 16 (depends on 13) The apparatus of claim 13, wherein a number of signals in the plurality of section signals is less than a number of signals in the plurality of sets of section sub signals. ### Claim 17 (depends on 13) The apparatus of claim 13, wherein a number of signals in the plurality of section signals is less than a number of sections expressed by the plurality of the first and second sets of section sub signals. ### Claim 18 (depends on 13) The apparatus of claim 13, wherein the size of each section of the plurality of sections corresponds to a number of word lines coupled to each section. ### Claim 19 (depends on 13) The apparatus of claim 13, wherein the first memory cell matrix includes a section among the plurality of sections and the second memory cell matrix includes two or more sections among the plurality of sections.