# US 12,224,036 B2 · High speed memory device with data masking

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- Number: US 12,224,036 B2
- Document ID: US12224036B2
- Status: Granted
- Kind: B2
- Application number: 17/447,827
- Filed: 2021-09-16
- Published: 2022-12-08
- Granted: 2025-02-11
- Earliest claimed: 2021-06-03
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Chunfei Deng; Shiyang Yang
- Web page: https://patentgrep.com/patent/US12224036B2

## CPC

- G11C 7/1009: {Data masking during input/output}
- G11C 16/10: Programming or data input circuits
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/1087: {Data input latches}
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 16/32: Timing circuits
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H03M 9/00: Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

Aspects of the disclosure provide a semiconductor device. For example, the semiconductor device can include a first deserializer, a second deserializer, and a write data converter coupled to the first deserializer and the second deserializer. The first deserializer can be configured to convert serial data to parallel data based on a set of write clock signals, thus the parallel data has a first timing alignment with regard to the set of write clock signals. The second deserializer can be configured to generate a mask pattern based on the set of write clock signals, thus the mask pattern has a second timing alignment with regard to the set of write clock signals. The write data converter can be configured to generate valid data based on the parallel data and the mask pattern.

## Claims

### Claim 1

A semiconductor device, comprising:
a first deserializer configured to convert serial data to parallel data with a first timing alignment with regard to a set of write clock signals;
a second deserializer configured to generate a mask pattern with a second timing alignment with regard to the set of write clock signals; and
a write data converter coupled to the first deserializer and the second deserializer, the write data converter configured to generate valid data based on the parallel data and the mask pattern, wherein the first deserializer outputs the parallel data and the second deserializer outputs the mask pattern at a same time,
wherein the first deserializer and the second deserializer are configured to have a same circuit structure that includes:
a sampling stage configured to sample a data input carrying the serial data based on a data strobe signal;
a first shift stage including a cascaded shift register path configured to shift the sampled serial data based on a first write clock signal and generate intermediate parallel data;
a second shift stage including parallel cascaded shift register paths to shift the intermediate parallel data based on a second write clock signal and generate the parallel data; and
an output stage configured to output the parallel data based on a third write clock signal.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first timing alignment and the second timing alignment allow the mask pattern being time-aligned with the parallel data.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising:
a clock generator coupled to the first deserializer and the second deserializer, the clock generator being configured to generate the set of write clock signals based on a data strobe signal.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the clock generator is configured to output the set of write clock signals with a timing pattern based on three least significant bits of an address signal, the timing pattern being used to control a loading time of the parallel data.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the clock generator includes:
a clock divider configured to generate a plurality of divided clock signals with frequencies divided from the data strobe signal; and
timing control circuitry coupled to the clock divider, the timing control circuitry configured to output, based on the divided clock signals, the set of write clock signals with the timing pattern.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the set of write clock signals based on which the first deserializer is configured to generate the parallel data is a same as the set of write clock signals based on which the second deserializer is configured to generate the mask pattern.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the second deserializer is configured to have a matching timing characteristic to the first deserializer.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the second deserializer is configured to have matching transistor delays to the first deserializer.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein the second deserializer is configured to have matching wire delays to the first deserializer.

### Claim 10

A method for masking data, comprising:
forming a first deserializer and a second deserializer of a same circuit structure;
converting serial data using the first deserializer to output parallel data based on a set of write clock signals, the parallel data having a first timing alignment with regard to the set of write clock signals;
outputting a mask pattern using the second deserializer based on the set of write clock signals, the mask pattern having a second timing alignment with regard to the set of write clock signals; and
combining the parallel data with the mask pattern to generate valid data,
wherein the first deserializer outputs the parallel data and the second deserializer outputs the mask pattern at a same time, and
wherein the same circuit structure includes:
a sampling stage configured to sample a data input carrying the serial data based on a data strobe signal;
a first shift stage including a cascaded shift register path configured to shift the sampled serial data based on a first write clock signal and generate intermediate parallel data;
a second shift stage including parallel cascaded shift register paths to shift the intermediate parallel data based on a second write clock signal and generate the parallel data; and
an output stage configured to output the parallel data based on a third write clock signal.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
time-aligning the mask pattern with the parallel data based on the first timing alignment and the second timing alignment.

### Claim 12 (depends on 10)

The method of claim 10, further comprising:
generating the set of write clock signals based on a data strobe signal.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
outputting the set of write clock signals with a timing pattern based on an address signal, the timing pattern being used to control a loading time of the parallel data.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
frequency-dividing the data strobe signal to generate a plurality of divided clock signals; and
outputting, based on the divided clock signals, the set of write clock signals with the timing pattern.

### Claim 15 (depends on 10)

The method of claim 10, wherein the set of write clock signals based on which the first deserializer is configured to generate the parallel data is a same as the set of write clock signals based on which the second deserializer is configured to generate the mask pattern.

### Claim 16 (depends on 10)

The method of claim 10, further comprising:
forming the second deserializer with matching timing characteristic to the first deserializer.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
forming the second deserializer with matching transistor delays to the first deserializer.

### Claim 18 (depends on 16)

The method of claim 16, further comprising:
forming the second deserializer with matching transistor delays to the first deserializer.

### Claim 19

A memory device, comprising:
a memory cell array configured to write data in parallel; and
peripheral circuitry comprising:
a first deserializer configured to convert serial data to parallel data with a first timing alignment with regard to a set of write clock signals;
a second deserializer configured to generate a mask pattern with a second timing alignment with regard to the set of write clock signals; and
a write data converter coupled to the first deserializer and the second deserializer, the write data converter configured to generate valid data for writing to the memory cell array by combining the parallel data with the mask pattern,
wherein the first deserializer outputs the parallel data and the second deserializer outputs the mask pattern at a same time, and the first deserializer and the second deserializer are configured to have a same circuit structure that includes:
a sampling stage configured to sample a data input carrying the serial data based on a data strobe signal;
a first shift stage including a cascaded shift register path configured to shift the sampled serial data based on a first write clock signal and generate intermediate parallel data;
a second shift stage including parallel cascaded shift register paths to shift the intermediate parallel data based on a second write clock signal and generate the parallel data; and
an output stage configured to output the parallel data based on a third write clock signal.

### Claim 20 (depends on 18)

The memory device of claim 18, wherein the memory device includes a three-dimensional NAND Flash memory device.