# US 12,224,032 B2 · Forwarding signal supply voltage in data transmission system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,032 B2 - Document ID: US12224032B2 - Status: Granted - Kind: B2 - Application number: 18/537,347 - Filed: 2023-12-12 - Published: 2024-06-06 - Granted: 2025-02-11 - Earliest claimed: 2009-08-31 - Assignees: Rambus Inc. - Applicants: Rambus Inc. - Inventors: Scott C. Best; John W. Poulton - Web page: https://patentgrep.com/patent/US12224032B2 ## CPC - G11C 5/144: {Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby} - G06F 11/0727: {in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097)} - G06F 11/076: {by exceeding a count or rate limit, e.g. word- or bit count limit} - G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)} - G06F 13/4072: {Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002)} - G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)} - H04L 1/203: {Details of error rate determination, e.g. BER, FER or WER} - H04L 25/0264: {Arrangements for coupling to transmission lines (duplexing arrangements H04L5/14; line equalisers, line build-out devices H04L25/03878)} - H04L 25/08: Modifications for reducing interference; Modifications for reducing effects due to line faults {; Receiver end arrangements for detecting or overcoming line faults} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit. ## Claims ### Claim 1 An integrated circuit comprising: transmitter circuitry configured to transmit, via a first external interface and to a controller integrated circuit that has voltage regulator circuitry configured to generate a signal supply voltage, a data signal that is to have a signal swing that is based on the signal supply voltage; and a second external interface configured to receive the signal supply voltage from the controller integrated circuit. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein adjustments of the signal supply voltage by the controller integrated circuit affect a bit error rate of the data signal as received by the controller integrated circuit. ### Claim 3 (depends on 2) The integrated circuit of claim 2, wherein the data signal is referenced to a power supply voltage and the data signal swings substantially symmetrically with respect to the power supply voltage. ### Claim 4 (depends on 3) The integrated circuit of claim 3, wherein the power supply voltage is a ground reference voltage. ### Claim 5 (depends on 4) The integrated circuit of claim 4, further comprising: receiver circuitry configured to receive a second signal having a second signal swing dependent on the signal supply voltage provided by the controller integrated circuit. ### Claim 6 (depends on 2) The integrated circuit of claim 2, wherein increasing the signal swing of the data signal by increasing the signal supply voltage is to decrease the bit error rate of the data signal as received by the controller integrated circuit. ### Claim 7 (depends on 2) The integrated circuit of claim 2, wherein decreasing the signal swing of the data signal by decreasing the signal supply voltage is to increase the bit error rate of the data signal as received by the controller integrated circuit. ### Claim 8 An integrated circuit, comprising: transmitter circuitry to transmit, to a controller integrated circuit comprising signal supply voltage regulator circuitry to produce a signal supply voltage, a first signal having a first signal swing based on the signal supply voltage; and a first external interface to receive, from the controller integrated circuit, the signal supply voltage. ### Claim 9 (depends on 8) The integrated circuit of claim 8, wherein the first signal is referenced to a power supply voltage and the first signal swings substantially symmetrically with respect to the power supply voltage. ### Claim 10 (depends on 9) The integrated circuit of claim 9, wherein the power supply voltage is a ground voltage. ### Claim 11 (depends on 8) The integrated circuit of claim 8, further comprising: receiver circuitry to receive a second signal having a second signal swing based on the signal supply voltage produced by the controller integrated circuit. ### Claim 12 (depends on 8) The integrated circuit of claim 8, wherein adjustments to the signal supply voltage produced by the controller integrated circuit affect a parameter indicative of signal integrity. ### Claim 13 (depends on 12) The integrated circuit of claim 12 wherein increasing the signal supply voltage improves the parameter indicative of signal integrity. ### Claim 14 (depends on 13) The integrated circuit of claim 13, wherein decreasing the signal supply voltage degrades the parameter indicative of signal integrity. ### Claim 15 An integrated circuit comprising: a first interface configured to receive a signal supply voltage generated by voltage regulator circuitry of a memory controller integrated circuit, the memory controller integrated circuit to produce a bit error rate indicator; and transmitter circuitry configured to transmit a data access signal, via a second external interface, that is to have a signal swing that is based on the signal supply voltage generated by the voltage regulator circuitry. ### Claim 16 (depends on 15) The integrated circuit of claim 15, wherein the data access signal is referenced to a power supply voltage and the data access signal swings substantially symmetrically with respect to the power supply voltage. ### Claim 17 (depends on 16) The integrated circuit of claim 16, wherein the power supply voltage is a ground reference voltage. ### Claim 18 (depends on 15) The integrated circuit of claim 15, further comprising: receiver circuitry configured to receive, via the second external interface, a second signal having a second signal swing dependent on the signal supply voltage generated by the voltage regulator circuitry. ### Claim 19 (depends on 15) The integrated circuit of claim 15, wherein the voltage regulator circuitry is to increase the signal supply voltage in response to the bit error rate indicator indicating a decrease in signal integrity. ### Claim 20 (depends on 19) The integrated circuit of claim 19, wherein the voltage regulator circuitry is to decrease the signal supply voltage in response to the bit error rate indicator indicating an increase in signal integrity.