# US 12,224,031 B2 · Semiconductor memory device

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- Number: US 12,224,031 B2
- Document ID: US12224031B2
- Status: Granted
- Kind: B2
- Application number: 18/071,118
- Filed: 2022-11-29
- Published: 2023-03-23
- Granted: 2025-02-11
- Earliest claimed: 2019-07-19
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Jung Dal Choi; Jung Shik Jang; Jin Kook Kim; Dong Sun Sheen; Se Young Oh; Ki Hong Lee; Dong Hun Lee; Sung Hoon Lee; Sung Yong Chung
- Web page: https://patentgrep.com/patent/US12224031B2

## CPC

- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/30: characterised by the memory core region
- H10B 43/35: with cell select transistors, e.g. NAND
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.

## Claims

### Claim 1

A semiconductor memory device comprising:
conductive patterns stacked apart from each other in a vertical direction, each of the conductive patterns including a first portion, a second portion spaced apart from the first portion and a third portion connecting the first portion and the second portion;
a hole passing through the conductive patterns, the hole including a sidewall surrounded by the first portion, the second portion and the third portion of each of the conducive patterns;
a first channel pattern disposed within the hole and adjacent to the first portion of each of the conducive patterns;
a second channel pattern disposed within the hole and adjacent to the second portion of each of the conducive patterns;
a single bit line connected to the first channel pattern and the second channel pattern; and
a channel separation pattern disposed within the hole and between the first channel pattern and the second channel pattern,
wherein each of the conductive patterns extends continuously from the first portion to the second portion without being separated by the channel separation pattern, and
wherein the first channel pattern and the second channel pattern are separated from each other by the channel separation pattern.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1,
wherein the single bit line has a longest dimension in a first direction, and
wherein the channel separation pattern has a longest dimension in a second direction crossing the first direction.

### Claim 3 (depends on 1)

The semiconductor memory device of claim 1, further comprising:
a contact plug disposed between the single bit line and the channel separation pattern and electrically connecting the first channel pattern and the second channel pattern to the single bit line.

### Claim 4 (depends on 3)

The semiconductor memory device of claim 3,
wherein the contact plug overlaps the channel separation pattern and extends to overlap the first channel pattern and the second channel pattern.

### Claim 5 (depends on 1)

The semiconductor memory device of claim 1, further comprising:
a first select line spaced apart from the conductive patterns in the vertical direction and overlapping the first portion of each of the conductive patterns;
a second select line spaced apart from the conductive patterns in the vertical direction and overlapping the second portion of each of the conductive patterns; and
a separation structure disposed between the first select line and the second select line.

### Claim 6 (depends on 5)

The semiconductor memory device of claim 5,
wherein the channel separation pattern overlaps the separation structure.

### Claim 7 (depends on 5)

The semiconductor memory device of claim 5,
wherein the single bit line has a longest dimension in a first direction, and
wherein the separation structure extends to be longer than the channel separation pattern in a second direction crossing the first direction.

### Claim 8 (depends on 5)

The semiconductor memory device of claim 5,
wherein the third portion of each of the conductive patterns extends to overlap the separation structure.

### Claim 9 (depends on 1)

The semiconductor memory device of claim 1, further comprising:
an upper select line spaced apart from the conductive patterns in the vertical direction and extending to overlap the first portion, the second portion and the third portion of each of the conductive patterns; and
a lower select line disposed between the upper select line and the conductive patterns and spaced apart from the upper select line and the conductive patterns,
wherein each of the hole, the first channel pattern, the second channel pattern and the channel separation pattern extends in the vertical direction to pass through the lower select line and the upper select line.

### Claim 10 (depends on 9)

The semiconductor memory device of claim 9,
wherein the first channel pattern includes a first channel region facing the lower select line and a second channel region facing the upper select line,
wherein the second channel pattern includes a third channel region facing the lower select line and a fourth channel region facing the upper select line, and
wherein threshold voltages of each of the first channel region and the fourth channel region are higher than threshold voltages of each of the second channel region and the third channel region.

### Claim 11 (depends on 1)

The semiconductor memory device of claim 1, further comprising:
a first memory pattern interposed between the first portion of each of the conductive patterns and the first channel pattern; and
a second memory pattern interposed between the second portion of each of the conductive patterns and the second channel pattern.

### Claim 12 (depends on 11)

The semiconductor memory device of claim 11,
wherein each of the first memory pattern and the second memory pattern includes a tunnel insulating film, a data storage film formed on a sidewall of the tunnel insulating film, and a blocking insulating film formed on the data storage film, and
wherein the channel separation pattern extends between the first memory pattern and the second memory pattern to pass through each of the tunnel insulating film, the data storage film and the blocking insulating film.

### Claim 13 (depends on 11)

The semiconductor memory device of claim 11,
wherein each of the first memory pattern and the second memory pattern includes a tunnel insulating film, a data storage film formed on a sidewall of the tunnel insulating film, and a blocking insulating film formed on the data storage film, and
wherein at least one of the tunnel insulating film, the data storage film and the blocking insulating film extends between the channel separation pattern and the third portion of each of the conductive patterns.

### Claim 14 (depends on 11)

The semiconductor memory device of claim 11,
wherein each of the first memory pattern and the second memory pattern includes a tunnel insulating film, a floating gate film formed on a sidewall of the tunnel insulating film, and a blocking insulating film formed on the floating gate film, and
wherein the channel separation pattern extends between the first memory pattern and the second memory pattern to pass through each of the tunnel insulating film, the floating gate film and the blocking insulating film.

### Claim 15 (depends on 11)

The semiconductor memory device of claim 11,
wherein each of the first memory pattern and the second memory pattern includes a tunnel insulating film, a floating gate film formed on a sidewall of the tunnel insulating film, and a blocking insulating film formed on the floating gate film,
wherein the channel separation pattern extends between the first memory pattern and the second memory pattern to pass through each of the tunnel insulating film and the floating gate film, and
wherein the blocking insulating film extends between the channel separation pattern and the third portion of each of the conductive patterns.