# US 12,224,030 B2 · Memory system

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,224,030 B2
- Document ID: US12224030B2
- Status: Granted
- Kind: B2
- Application number: 17/987,435
- Filed: 2022-11-15
- Published: 2023-06-22
- Granted: 2025-02-11
- Earliest claimed: 2021-12-17
- Assignees: Windbond Electronics Corp.
- Applicants: Winbond Electronics Corp.
- Inventors: Takahiko Sato
- Web page: https://patentgrep.com/patent/US12224030B2

## CPC

- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals}
- G11C 7/109: {Control signal input circuits}
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 2029/0409: {Online test}
- G11C 2029/0411: {Online error correction}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

The present invention provides a memory system in which a semiconductor memory device can be accessed properly. The memory system includes a memory controller and a semiconductor memory device. The memory controller sends a command, an address, and first checking data to the semiconductor memory device. When the semiconductor memory device receives first response information that indicates that no error has been detected, it sends or receives read data or write data from the semiconductor memory device. When the semiconductor memory device receives the command, the address, and the first checking data, it uses the first checking data to detect errors in the command and the address, and sends the first reply information when no error is detected, and when no error is detected in the command and the address, it sends or receives read data or write data from the semiconductor memory device.

## Claims

### Claim 1

A memory system, comprising:
a memory controller; and
a semiconductor memory device;
wherein the memory controller is configured to:
send a command, an address and first check data for error detection of the command and the address to the semiconductor memory device; and
when receiving first response information indicating that no error has been detected in the command and the address from the semiconductor memory device, based on the command, send to or receive from the semiconductor memory device of data to be read from or written into the address;
wherein the semiconductor memory device is configured to:
when receiving the command, the address and the first check data from the memory controller, use the first check data to perform error detection of the command and the address, and send the first response information to the memory controller when no error is detected in the command and the address; and
when no error is detected in the command and the address, based on the command, send to or receive from the memory controller of the data to be read from or written into the address;
wherein the memory controller or the semiconductor memory device is configured to:
send the data to be read or write and second check data for error detection of the data to the other of the memory controller or the semiconductor memory device; and
the other of the memory controller or the semiconductor memory device is configured to:
when receiving the data and the second check data, use the second check data to perform error detection of the data, and send third response information indicating that no error has been detected in the data to the memory controller and the semiconductor memory device.

### Claim 2 (depends on 1)

The memory system as claimed in claim 1, wherein the semiconductor memory device is configured to:
when an error is detected in the command or the address, send second response information indicating that an error has been detected in the command or the address to the memory controller;
wherein the memory controller is configured to:
when receiving the second response information from the semiconductor memory device, re-send the command and the address to the semiconductor memory device.

### Claim 3 (depends on 1)

The memory system as claimed in claim 1, wherein:
the other of the memory controller or the semiconductor memory device is configured to:
when an error is detected in the data, send fourth response information indicating that an error has occurred in the data to the memory controller or the semiconductor memory device; and
wait for a re-sending of the data from the memory controller or the semiconductor memory device until a specific time duration elapses.

### Claim 4 (depends on 3)

The memory system as claimed in claim 3, wherein:
the memory controller or the semiconductor memory device is configured to:
when receiving the fourth response information, re-send the data and the second check data corresponding to the data to the other of the memory controller or the semiconductor memory device.

### Claim 5 (depends on 3)

The memory system as claimed in claim 3, wherein:
the other of the memory controller or the semiconductor memory device is configured to:
terminate the waiting for the data to be re-sent when the data is not re-sent from the memory controller or the semiconductor memory device until the specific time duration has elapsed.

### Claim 6 (depends on 1)

The memory system as claimed in claim 1, wherein the semiconductor memory device further comprises a plurality of memory banks accessed in an interleaved manner.

### Claim 7 (depends on 1)

The memory system as claimed in claim 1, wherein when the semiconductor memory device is configured to generate an update request signal internally for executing an update, the semiconductor memory device is configured to:
in the duration between the generation of the update request signal and the execution of the update,
upon an error being detected in the command, the address, or the data received from the memory controller,
stop the execution of the update by re-sending the command, the address, or the data from the memory controller until no error is detected.

### Claim 8 (depends on 1)

The memory system as claimed in claim 1, wherein when the semiconductor memory device is configured to generate an update request signal internally for executing an update, the semiconductor memory device is configured to:
in the duration between the generation of the update request signal and the execution of the update,
upon an error being detected in the command, the address, or the data received from the memory controller,
send fifth response information indicating that the update is executed to the memory controller, and
execute the update.

### Claim 9 (depends on 1)

The memory system as claimed in claim 1, wherein the semiconductor memory device is a pseudo-static random access memory.

### Claim 10

A memory system, comprising:
a memory controller;
a semiconductor memory device;
wherein the memory controller is configured to:
send a command, an address and first check data for error detection of the command and the address to the semiconductor memory device; and
when receiving first response information indicating that no error has been detected in the command and the address from the semiconductor memory device, based on the command, send to or receive from the semiconductor memory device of data to be read from or written into the address;
wherein the semiconductor memory device is configured to:
when receiving the command, the address and the first check data from the memory controller, use the first check data to perform error detection of the command and the address, and send the first response information to the memory controller when no error is detected in the command and the address; and
when no error is detected in the command and the address, based on the command, send to or receive from the memory controller of the data to be read from or written into the address;
a request control part, generating a transform signal upon receiving a request for writing to or reading from the semiconductor memory device from a host device, wherein the transform signal transforms a transmitting mode of an address data signal sending and receiving between the memory controller and the semiconductor memory device; and
a first serial control part, transforming the transmitting mode of the address data signal based on the transform signal.

### Claim 11 (depends on 10)

The memory system as claimed in claim 10, wherein the first serial control part comprises:
a first serializer/deserializer, serializing or deserializing the address data signal based on the transform signal; and
a first error control part, using the command and the address to generate the first check data.

### Claim 12 (depends on 11)

The memory system as claimed in claim 11, wherein the first serializer/deserializer is configured to:
when the request control part receives a write request, upon the transform signal being input from the request control part, generate a write command and the address, and send the write command and the address to the first error control part;
in response to the first check data of the generated write command and the address being input from the first error control part, send the generated write command, the address and the first check data to the semiconductor memory device as the address data signal; and
when receiving the first response information indicating that no error has been detected in the generated write command and the address from the semiconductor memory device as the address data signal, output data-to-be-written received from the host device to the first error control part.

### Claim 13 (depends on 10)

The memory system as claimed in claim 10, wherein the first error control part is configured to use the data-to-be-written to generate second check data for error detection of the data-to-be-written; and
wherein the first serializer/deserializer is configured to send the second check data and the data-to-be-written to the semiconductor memory device as the address data signal when the second check data is input from the first error control part.

### Claim 14 (depends on 10)

The memory system as claimed in claim 10, wherein the first error control part is configured to generate a signal for re-sending the write command, the address and the first check data, upon receiving the second response information indicating that an error has been detected in the write command or the address as the address data signal.

### Claim 15 (depends on 14)

The memory system as claimed in claim 14, wherein the first serializer/deserializer is configured to, when receiving the second response information from the semiconductor memory device as the address data signal, upon the signal for re-sending the write command, the address and the first check data being input from the first error control part, re-send the write command, the address and the first check data to the semiconductor memory device as the address data signal.

### Claim 16 (depends on 10)

The memory system as claimed in claim 10, wherein the semiconductor memory device further comprises a second serial control part, transforming the transmission mode of the address data signal sent to or received from the memory controller;
wherein the second serial control part comprises:
a second serializer/deserializer, to serialize or deserialize the address data signal; and
a second error control part, using the first check data received from the memory controller to perform error detection of the command and the address.

### Claim 17 (depends on 16)

The memory system as claimed in claim 16, wherein the second serializer/deserializer is configured to:
when receiving the command, the address and the first check data from the memory controller as the address data signal, transform the command, the address and the first check data into a serial transmission mode, and output the command, the address and the first check data to the second error control part;
when the first response information is input from the second error control part, transform the first response information into a parallel transmission mode, output the first response information to the memory controller as the address data signal, output a signal indicating the content of the command to a command control part which generates an internal command based on the command, and output a signal indicating the address to an address control part which controls an activation of a word line and a bit line corresponding to the address; and
when the second response information is input from the second error control part, transform the second response information into the parallel transmission mode, and send the second response information to the memory controller as the address data signal.

### Claim 18 (depends on 16)

The memory system as claimed in claim 16, wherein:
the second error control part is configured to use the second check data for error detection of the data-to-be-written to perform error detection of the data-to-be-written; and
the second serializer/deserializer is configured to:
when receiving the data-to-be-written and the second check data for error detection of the data-to-be-written from the memory controller as the address data signal, output the data-to-be-written and the second check data to the second error control part; and
when the fourth response information indicating that an error has been detected in the data-to-be-written is input from the second error control part, send the fourth response information to the memory controller as the address data signal.

### Claim 19

A memory system, comprising:
a memory controller; and
a semiconductor memory device;
wherein the memory controller is configured to:
send a command, an address and first check data for error detection of the command and the address to the semiconductor memory device; and
when receiving first response information indicating that no error has been detected in the command and the address from the semiconductor memory device, based on the command, send to or receive from the semiconductor memory device of data to be read from or written into the address;
wherein the semiconductor memory device is configured to:
when receiving the command, the address and the first check data from the memory controller, use the first check data to perform error detection of the command and the address, and send the first response information to the memory controller when no error is detected in the command and the address; and
when no error is detected in the command and the address, based on the command, send to or receive from the memory controller of the data to be read from or written into the address;
wherein when the semiconductor memory device is configured to generate an update request signal internally for executing an update, the semiconductor memory device is configured to:
in the duration between the generation of the update request signal and the execution of the update,
upon an error being detected in the command, the address, or the data received from the memory controller,
stop the execution of the update by re-sending the command, the address, or the data from the memory controller until no error is detected.

### Claim 20 (depends on 19)

The memory system as claimed in claim 19, wherein when the semiconductor memory device is configured to generate an update request signal internally for executing an update, the semiconductor memory device is configured to:
in the duration between the generation of the update request signal and the execution of the update,
upon an error being detected in the command, the address, or the data received from the memory controller,
send fifth response information indicating that the update is executed to the memory controller, and
execute the update.