# US 12,224,026 B2 · Semiconductor memory device and memory system performing error correction operation

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- Number: US 12,224,026 B2
- Document ID: US12224026B2
- Status: Granted
- Kind: B2
- Application number: 18/101,123
- Filed: 2023-01-25
- Published: 2024-05-16
- Granted: 2025-02-11
- Earliest claimed: 2022-11-10
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Hong Ki Moon
- Web page: https://patentgrep.com/patent/US12224026B2

## CPC

- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/18: Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C 29/46: Test trigger logic
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 2029/0411: {Online error correction}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor memory device includes a command address control circuit configured to generate an error correction command and selection address for executing an error correction operation by receiving an external control signal, an error flag generation circuit configured to correct an error of data corresponding to the selection address and configured to generate a target error flag based on a pattern of the error of the data, and an error information processing circuit configured to generate a target address that is used as the selection address based on the target error flag in a target error correction operation that is executed based on the error correction operation.

## Claims

### Claim 1

A semiconductor memory device comprising:
a command address control circuit configured to generate, in response to an external control signal, an error correction command and a selection address for executing an error correction operation;
an error flag generation circuit configured to execute the error correction operation by correcting an error of data corresponding to the selection address and configured to generate a target error flag based on a predetermined pattern of the error that occurred previously in the error correction operation and which is indicative of a problem in an operation of the semiconductor memory device; and
an error information processing circuit configured to generate, based on the target error flag, a target address that is used as the selection address for a target error correction operation that is executed when the error correction operation is executed a predetermined number of times.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein the target error correction operation is set to be repeatedly executed whenever the error correction operation is executed the predetermined number of times.

### Claim 3 (depends on 2)

The semiconductor memory device of claim 2, wherein:
the command address control circuit comprises a command control circuit configured to generate one of a selection error correction command and a target selection command in response to the error correction command, and
the command control circuit is configured to generate the selection error correction command by the predetermined number in response to the error correction command and then generate the target selection command in response to the error correction command.

### Claim 4 (depends on 3)

The semiconductor memory device of claim 3, wherein:
the command address control circuit is further configured to adjust the predetermined number based on a first test mode signal, and
the first test mode signal is generated based on at least one of an internal temperature, data usage, an error occurrence ratio, or a set signal that is stored in a mode register included in the semiconductor memory device.

### Claim 5 (depends on 3)

The semiconductor memory device of claim 3, wherein the command address control circuit further includes an address counter configured to generate a counting address by counting the selection error correction command.

### Claim 6 (depends on 5)

The semiconductor memory device of claim 5, wherein the command address control circuit further includes an address selection circuit configured to output one of the counting address and the target address as the selection address in response to the target selection command.

### Claim 7 (depends on 1)

The semiconductor memory device of claim 1, wherein the error flag generation circuit comprises:
a data storage circuit configured to store the data, and
a parity storage circuit configured to store a parity that is generated based on the data.

### Claim 8 (depends on 7)

The semiconductor memory device of claim 7, wherein the error flag generation circuit includes:
an error correction circuit configured to generate a syndrome from the data corresponding to the selection address and the parity and configured to generate an error flag by determining the error based on the syndrome; and
a target error detection circuit configured to generate the target error flag by determining the pattern of the error based on the syndrome.

### Claim 9 (depends on 8)

The semiconductor memory device of claim 8, wherein:
the error correction circuit generates the error flag when the error occurs, and
the target error detection circuit generates the target error flag when the error has the predetermined pattern.

### Claim 10 (depends on 9)

The semiconductor memory device of claim 9, wherein the predetermined pattern is the error occurred from memory cells of the data storage circuit and the memory cells is located adjacent to the parity storage circuit.

### Claim 11 (depends on 1)

The semiconductor memory device of claim 1, wherein the error information processing circuit includes a flag detection circuit configured to generate an error detection signal and a target error detection signal based on an error flag and the target error flag and configured to generate an error pulse when the error flag is generated.

### Claim 12 (depends on 11)

The semiconductor memory device of claim 11, wherein the error information processing circuit further includes an error counter configured to generate an error counting signal by counting the error pulse.

### Claim 13 (depends on 12)

The semiconductor memory device of claim 12, wherein the error information processing circuit further includes an error information storage circuit configured to store the selection address and the error counting signal as error information in response to the error detection signal and the target error detection signal.

### Claim 14 (depends on 13)

The semiconductor memory device of claim 13, wherein the error information processing circuit further includes an error information input and output (I/O) control circuit configured to generate the target address based on selection error information that is included in the error information stored in the error information storage circuit and that is selected by an information selection signal.

### Claim 15 (depends on 14)

The semiconductor memory device of claim 14, wherein the error information I/O control circuit is further configured to receive information with regard to the target address through a data pad in response to a third test mode signal.

### Claim 16 (depends on 14)

The semiconductor memory device of claim 14, wherein the error information I/O control circuit is further configured to sequentially output, as the target address, the error information that has been stored in the error information storage circuit.

### Claim 17 (depends on 14)

The semiconductor memory device of claim 14, wherein the error information I/O control circuit is further configured to output the selection error information through the data pad in response to a mode register read command.

### Claim 18

A memory system comprising:
a semiconductor memory device; and
a memory controller configured to control the semiconductor memory device,
wherein the semiconductor memory device is configured to:
generate a selection address so that an error correction operation for a counting address or a target error correction operation for a target address is selectively executed in response to a control signal that is provided by the memory controller, and
generate the target address when an error corrected through the error correction operation is a target error having a predetermined pattern that occurred previously in the error correction operation and which is indicative of a problem in an operation of the semiconductor memory device.

### Claim 19 (depends on 18)

The memory system of claim 18, wherein:
the semiconductor memory device comprises a command control circuit configured to generate one of a selection error correction command and a target command in response to an error correction command, and
the command control circuit is configured to generate the selection error correction command by a predetermined number in response to the error correction command and then generate a target selection command in response to the error correction command.

### Claim 20 (depends on 18)

The memory system of claim 18, wherein the semiconductor memory device is further configured to determine whether the error corrected through the error correction operation is the target error having the predetermined pattern, based on a syndrome that is generated based on data and a parity that correspond to the selection address.

### Claim 21 (depends on 20)

The memory system of claim 20, wherein the target error is the error corrected through the error correction operation is included in the data and occurred from memory cells adjacent to a parity storage circuit included in the semiconductor memory device.

### Claim 22 (depends on 18)

The memory system of claim 18, wherein the semiconductor memory device is further configured to:
adjust the predetermined number in response to a first signal that is provided by the memory controller,
receive, from the memory controller, information for generating the target address in response to a second signal, and
provide the memory controller with information that is related to the target address, in response to a third signal.

### Claim 23

A method of executing an error correction operation, comprising:
transmitting a control signal from a memory controller to a semiconductor memory device in order to execute an error correction operation;
selecting, as a target address, an address in which a corrected error has occurred when the error, which is corrected through the error correction operation executed by the semiconductor memory device, has a predetermined pattern that occurred previously in the error correction operation and which is indicative of a problem in an operation of the semiconductor memory device; and
executing a target error correction operation on the target address after the error correction operation is executed for a predetermined number of times.

### Claim 24 (depends on 23)

The method of claim 23, wherein the error correction operation comprises:
correcting the error based on a syndrome that is generated based on data and a parity; and
determining whether the error has the predetermined pattern based on the syndrome.

### Claim 25 (depends on 23)

The method of claim 23, further comprising transmitting the target address to the memory controller through a data pad.

### Claim 26 (depends on 23)

The method of claim 23, wherein the predetermined pattern is the error is occurred from memory cells adjacent to a parity storage circuit included in the semiconductor memory device.

### Claim 27

An operating method of a memory device, the operating method comprising:
performing a first error correcting operation on a region of memory cells included therein, the error correcting operation including collecting information of a predetermined location, wherein the information is indicative of a problem in an operation of the semiconductor memory device, from which an error is detected within the region; and
performing, after completing a predetermined number of times of the first error correcting operation to identify the predetermined location in the region of memory cells, a second error correcting operation on the predetermined location based on the collected information to improve reliability of data stored in the predetermined location.