# US 12,224,021 B2 · Memory device with leakage current verifying circuit for minimizing leakage current

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- Number: US 12,224,021 B2
- Document ID: US12224021B2
- Status: Granted
- Kind: B2
- Application number: 18/469,567
- Filed: 2023-09-19
- Published: 2024-01-04
- Granted: 2025-02-11
- Earliest claimed: 2021-05-31
- Assignees: Winbond Electronics Corp.
- Applicants: Winbond Electronics Corp.
- Inventors: Koying Huang
- Web page: https://patentgrep.com/patent/US12224021B2

## CPC

- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/16: for erasing blocks, e.g. arrays, words, groups
- G11C 16/24: Bit-line control circuits
- G11C 16/30: Power supply circuits
- G11C 16/344: {Arrangements for verifying correct erasure or for detecting overerased cells}
- G11C 16/3454: {Arrangements for verifying correct programming or for detecting overprogrammed cells}
- G11C 29/50: Marginal testing, e.g. race, voltage or current testing
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/28: using differential sensing or reference cells, e.g. dummy cells
- G11C 2029/5006: {Current}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device includes a controller configured for initiating a program operation for a first column of memory cells which belongs to a group of memory cells; setting a verify condition which comprises a leakage current threshold during a leakage current verifying operation; performing, via a leakage current verifying circuit, a leakage current verifying operation for the first column of the memory cells by applying a negative voltage sweep to each of first remaining M−1 unselected WLs of the M WLs until finding a first negative voltage resulting in the first column of the memory cells having passed leakage current threshold; and applying the program operation for the first column of the memory cells by applying the first negative voltage to each of the first remaining M−1 unselected WLs of the M WLs and a positive bit line voltage for the N BLs.

## Claims

### Claim 1

A memory device comprising:
a memory array comprising a group of memory cells which comprises M word lines (WLs) and N bit lines as M and N are integers greater than 1;
a leakage current verifying circuit for verifying leakage currents of the memory array; and
a controller coupled to the memory array and the leakage current verifying circuit and configured at least to:
initiate a program operation for a first column of memory cells which belongs to the group of memory cells and is connected to a first WL of the M WLs;
set a verify condition which comprises a leakage current threshold during a leakage current verifying operation;
perform, via the leakage current verifying circuit, a leakage current verifying operation for the first column of the memory cells by applying a negative voltage sweep to each of first remaining M−1 unselected WLs of the M WLs until finding a first negative voltage resulting in the first column of the memory cells having passed leakage current threshold;
apply the program operation for the first column of the memory cells by applying the first negative voltage to each of the first remaining M−1 unselected WLs of the M WLs and a positive bit line voltage for the N BLs;
determine whether a first address corresponding to the first column of the memory cells is a final address;
initiate the program operation for a second column of memory cells which belongs to the group of memory cells and is connected to a second WL of the M WLs in response to the first address not being the final address;
select the second WL of the M WLs corresponding to the second column of the memory cells;
apply another negative voltage sweep to each of a second remaining M−1 unselected WLs of the M WLs until finding a second negative voltage resulting in the second column of the memory cells passing the leakage current threshold, wherein the first negative voltage is different from the second negative voltage;
apply the program operation for the second column of the memory cells while applying the second negative voltage to each of the second remaining M−1 unselected WLs of the M WLs;
apply a negative voltage for the first remaining M−1 unselected WLs of the M WLs;
determine whether the first column of the memory cells passes the leakage current threshold;
in response to the first column of the memory cells passing the leakage current threshold, selecting the negative voltage as the first negative voltage; and
in response to the first column of the memory cells not passing the leakage current threshold, keep decreasing the negative voltage until the first column of the memory cells passes the leakage current threshold, wherein the leakage current verify circuit comprises:
a sense amplifier circuit configured to compare a leakage current of the cell of the first column of the memory cells to a reference current source which serves as the leakage current threshold, and
a buffer amplifier configured to transmit a binary signal which indicates either the passing of the first column of the memory cells or the failure of the first column of the memory cells.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the leakage current verify circuit further comprises:
an OR gate connected to each cell of the first column of the memory cells for indicating whether any cell of the first column of memory cells has failed the leakage current verifying operation.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the leakage current verify circuit further comprises a WL voltage regulating circuit for regulating a negative voltage for each of the first remaining M−1 unselected WLs.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein the WL voltage regulating circuit comprises:
a first resistor (R1) receiving a constant voltage from a buffer amplifier; and
an adjustable second resistor (R2) connected to the R1 in series and a WL of the M WLs.

### Claim 5 (depends on 3)

The memory device of claim 3, wherein the negative voltage for each of the first remaining M−1 unselected WLs is regulated according to −(R2/R1).

### Claim 6 (depends on 3)

The memory device of claim 3, wherein the WL voltage regulating circuit further comprises:
a third resistor (R3);
a voltage follower amplifier;
a comparator amplifier; and
a N type transistor.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein a first terminal of the first resistor is connected to the voltage follower amplifier, and a second terminal of the first resistor is connected to the comparator amplifier, the N type transistor, and the third resistor.

### Claim 8 (depends on 7)

The memory device of claim 7, wherein a first terminal of the second resistor is connected to a negative voltage charge pump, and a second terminal of the second resistor is connected to the N type transistor and the third resistor.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein the second terminal of the second resistor is connected to the WLs of memory cells and thus may output a regulated negative voltage to unselected WLs during a post program verify operation.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein a regulated negative voltage at the second terminal of the second resistor is regulated according to −(R2/R1+Vth) where Vth is a threshold voltage of the N type transistor.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein higher temperature causes Vth to decrease so as to cause the regulated negative voltage to decrease.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein higher temperature causes less current to flow through the N type transistor so as to cause the second terminal of the second resistor to output a lesser regulated negative voltage.

### Claim 13 (depends on 11)

The memory device of claim 11, wherein the regulated negative voltage at the second terminal of the second resistor is regulated according to −((R2/R1)+(R3/R1)).

### Claim 14 (depends on 13)

The memory device of claim 13, wherein R1 and R2 have higher doping resistances than R3.

### Claim 15 (depends on 7)

The memory device of claim 7, wherein the third resistor is connected in parallel with the N type transistor, and the first and the second terminals of the third resistor are connected to the second terminal of the first resistor and the first terminal of the second resistor respectively.