# US 12,224,016 B2 · Transient and stable state read operations of a memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,016 B2 - Document ID: US12224016B2 - Status: Granted - Kind: B2 - Application number: 17/888,781 - Filed: 2022-08-16 - Published: 2024-02-22 - Granted: 2025-02-11 - Earliest claimed: 2022-08-16 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Ugo Russo; Karan Banerjee; Shyam Sunder Raghunathan - Web page: https://patentgrep.com/patent/US12224016B2 ## CPC - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/32: Timing circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory system may implement a read operation including a delay if a channel is at stable state, and may implement a read operation without a delay if the channel is in a transient state. Upon receiving a read command to a set of memory cells sharing the channel, the memory system may determine whether the channel is in a stable or transient state. If the channel is in a stable state, the memory system may perform a read operation including a delay between boosting the channel and driving respective word lines, such that the channel partially discharges prior to driving the word lines. If the channel is in a transient state, the memory system may perform a read operation without a delay between boosting the channel and driving the word lines. ## Claims ### Claim 1 A method, comprising: receiving, at a memory system, a first read command associated with a first memory cell of a first set of memory cells, wherein the first set of memory cells comprises a first channel; reading the first memory cell using a first type of read operation based on determining that the first channel comprises a first voltage condition, wherein the first type of read operation includes a delay associated with discharging at least a portion of a charge on the first channel over a first duration, and wherein the first voltage condition is based at least in part on a duration since a previous read operation performed on the first set of memory cells; receiving a second read command associated with a second memory cell of a second set of memory cells, wherein the second set of memory cells comprises a second channel; and reading the second memory cell using a second type of read operation based on determining that the second channel comprises a second voltage condition, wherein the second type of read operation refrains from including the delay. ### Claim 2 (depends on 1) The method of claim 1, wherein reading the first memory cell using the first type of read operation further comprises: driving respective word lines associated with the first set of memory cells from a first voltage to a second voltage at a first time; and maintaining, for the first duration after the first time, a word line coupled with the first memory cell at the second voltage based at least in part on determining that the first channel comprises the first voltage condition. ### Claim 3 (depends on 2) The method of claim 2, wherein reading the first memory cell using the first type of read operation comprises: driving, after the first duration, the word line coupled with the first memory cell from the second voltage to a third voltage. ### Claim 4 (depends on 2) The method of claim 2, wherein maintaining the word line coupled with the first memory cell at the second voltage comprises: floating, during the first duration, the word line coupled with the first memory cell. ### Claim 5 (depends on 1) The method of claim 1, wherein reading the second memory cell using the second type of read operation further comprises: driving respective word lines associated with the second set of memory cells from a fourth voltage to a fifth voltage at a second time; and maintaining, for a second duration after the second time, a word line coupled with the second memory cell at the fifth voltage based at least in part on determining that the second channel comprises the second voltage condition, wherein the second duration is less than the first duration. ### Claim 6 (depends on 5) The method of claim 5, wherein reading the second memory cell using the second type of read operation comprises: driving, after the second duration, the word line coupled with the second memory cell from the fifth voltage to a sixth voltage. ### Claim 7 (depends on 1) The method of claim 1, wherein the first read command comprises a first type of read command associated with including the delay and the second read command comprises a second type of read command associated with refraining to include the delay. ### Claim 8 (depends on 1) The method of claim 1, wherein determining that the first channel comprises the first voltage condition comprises: determining that a quantity of reads performed on the first set of memory cells within a third duration does not satisfy a threshold. ### Claim 9 (depends on 1) The method of claim 1, wherein determining that the second channel comprises the second voltage condition comprises: determining that a quantity of reads performed on the second set of memory cells within a fourth duration satisfies a threshold. ### Claim 10 (depends on 9) The method of claim 9, wherein determining that the quantity of reads performed on the second set of memory cells within the fourth duration satisfies the threshold comprises: storing respective times of previous accesses of a plurality of sets of memory cells, the plurality of sets of memory cells comprising the second set of memory cells. ### Claim 11 (depends on 1) The method of claim 1, wherein determining that the second channel comprises the second voltage condition comprises: determining that the second read command is from a plurality of read commands issued to the second set of memory cells. ### Claim 12 (depends on 1) The method of claim 1, wherein reading the first memory cell using the first type of read operation comprises: discharging the first channel to below a threshold voltage prior to reading the first memory cell based at least in part on determining that the first channel comprises the first voltage condition. ### Claim 13 A memory system, comprising: one or more memory devices; and one or more controllers coupled with the one or more memory devices and configured to cause the memory system to: receive, at the memory system, a first read command associated with a first memory cell of a first set of memory cells, wherein the first set of memory cells comprises a first channel; read the first memory cell using a first type of read operation based at least in part on determining that the first channel comprises a first voltage condition, wherein the first type of read operation comprises including a delay associated with discharging at least a portion of a charge on the first channel over a first duration, and wherein the first voltage condition is based at least in part on a duration since a previous read operation performed on the first set of memory cells; receive a second read command associated with a second memory cell of a second set of memory cells, wherein the second set of memory cells comprises a second channel; and read the second memory cell using a second type of read operation based at least in part on determining that the second channel comprises a second voltage condition, wherein the second type of read operation comprises refraining from including the delay. ### Claim 14 (depends on 13) The memory system of claim 13, wherein reading the first memory cell using the first type of read operation is further configured to cause the memory system to: drive respective word lines associated with the first set of memory cells from a first voltage to a second voltage at a first time; and maintain, for the first duration after the first time, a word line coupled with the first memory cell at the second voltage based at least in part on determining that the first channel comprises the first voltage condition. ### Claim 15 (depends on 14) The memory system of claim 14, wherein reading the first memory cell using the first type of read operation is configured to cause the memory system to: drive, after the first duration, the word line coupled with the first memory cell from the second voltage to a third voltage. ### Claim 16 (depends on 14) The memory system of claim 14, wherein maintaining the word line coupled with the first memory cell at the second voltage is configured to cause the memory system to: float, during the first duration, the word line coupled with the first memory cell. ### Claim 17 (depends on 13) The memory system of claim 13, wherein reading the second memory cell using the second type of read operation is further configured to cause the memory system to: drive respective word lines associated with the second set of memory cells from a fourth voltage to a fifth voltage at a second time; and maintain, for a second duration after the second time, a word line coupled with the second memory cell at the fifth voltage based at least in part on determining that the second channel comprises the second voltage condition, wherein the second duration is less than the first duration. ### Claim 18 (depends on 17) The memory system of claim 17, wherein reading the second memory cell using the second type of read operation is configured to cause the memory system to: drive, after the second duration, the word line coupled with the second memory cell from the fifth voltage to a sixth voltage. ### Claim 19 (depends on 13) The memory system of claim 13, wherein the first read command comprises a first type of read command associated with including the delay and the second read command comprises a second type of read command associated with refraining to include the delay. ### Claim 20 (depends on 13) The memory system of claim 13, wherein determining that the first channel comprises the first voltage condition is configured to cause the memory system to: determine that a quantity of reads performed on the first set of memory cells within a third duration does not satisfy a threshold. ### Claim 21 (depends on 13) The memory system of claim 13, wherein determining that the second channel comprises the second voltage condition is configured to cause the memory system to: determine that a quantity of reads performed on the second set of memory cells within a fourth duration satisfies a threshold. ### Claim 22 (depends on 21) The memory system of claim 21, wherein determining that the quantity of reads performed on the second set of memory cells within the fourth duration satisfies the threshold is configured to cause the memory system to: store respective times of previous accesses of a plurality of sets of memory cells, the plurality of sets of memory cells comprising the second set of memory cells. ### Claim 23 (depends on 13) The memory system of claim 13, wherein determining that the second channel comprises the second voltage condition is configured to cause the memory system to: determine that the second read command is from a plurality of read commands issued to the second set of memory cells. ### Claim 24 (depends on 13) The memory system of claim 13, wherein reading the first memory cell using the first type of read operation is configured to cause the memory system to: discharge the first channel to below a threshold voltage prior to reading the first memory cell based at least in part on determining that the first channel comprises the first voltage condition. ### Claim 25 A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to: receive, at a memory system, a first read command associated with a first memory cell of a first set of memory cells, wherein the first set of memory cells comprises a first channel; read the first memory cell using a first type of read operation based at least in part on determining that the first channel comprises a first voltage condition, wherein the first type of read operation comprises including a delay associated with discharging at least a portion of a charge on the first channel over a first duration, and wherein the first voltage condition is based at least in part on a duration since a previous read operation performed on the first set of memory cells; receive a second read command associated with a second memory cell of a second set of memory cells, wherein the second set of memory cells comprises a second channel; and read the second memory cell using a second type of read operation based at least in part on determining that the second channel comprises a second voltage condition, wherein the second type of read operation comprises refraining from including the delay.