# US 12,224,013 B2 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,013 B2 - Document ID: US12224013B2 - Status: Granted - Kind: B2 - Application number: 18/183,008 - Filed: 2023-03-13 - Published: 2024-03-21 - Granted: 2025-02-11 - Earliest claimed: 2022-09-15 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Jae Woong Kim - Web page: https://patentgrep.com/patent/US12224013B2 ## CPC - G11C 16/102: {External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/32: Timing circuits - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/30: characterised by the memory core region - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor memory device includes a channel layer coupled to a bit line, a cell string located along a first side portion of the channel layer, and an auxiliary string located along a second side portion of the same channel layer. ## Claims ### Claim 1 A semiconductor memory device, comprising: a memory cell array comprising a cell string and an auxiliary string, which are coupled to each other through a channel layer that is coupled to a bit line, wherein the cell string comprises a plurality of memory cells stacked along a first side portion of the channel layer and wherein the auxiliary string comprises a plurality of auxiliary transistors stacked along a second side portion of the channel layer; and a voltage supply circuit configured to apply a first pass voltage to an unselected auxiliary word line among a plurality of auxiliary word lines coupled to the plurality of auxiliary transistors and, apply a first voltage, which is less than the first pass voltage, to an unselected word line among the plurality of word lines coupled to the plurality of memory cells while applying a program voltage or a read voltage to the selected word line among the plurality of word lines. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein the unselected auxiliary word line is disposed at a substantially same level as the unselected word line. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein the voltage supply circuit is configured to apply a second voltage to a selected auxiliary word line provided at a substantially same level as the selected word line among the plurality of auxiliary word lines while applying the program voltage to the selected word line, and wherein the second voltage is less than the first pass voltage. ### Claim 4 (depends on 3) The semiconductor memory device according to claim 3, wherein the voltage supply circuit is configured to supply a ground voltage or a positive voltage, as the second voltage, while applying the program voltage to the selected word line. ### Claim 5 (depends on 3) The semiconductor memory device according to claim 3, wherein the voltage supply circuit is configured to: apply a second pass voltage to the selected word line before applying the program voltage to the selected word line, and supply the second voltage as a voltage less than the second pass voltage. ### Claim 6 (depends on 3) The semiconductor memory device according to claim 3, wherein the voltage supply circuit is configured to: apply a second pass voltage to the selected word line before applying the program voltage to the selected word line, and supply at least one of: a ground voltage and a positive voltage less than the second pass voltage, as the first voltage, while applying the program voltage to the selected word line. ### Claim 7 (depends on 3) The semiconductor memory device according to claim 3, wherein the voltage supply circuit is configured to: apply a second pass voltage to the selected word line before applying the program voltage to the selected word line, and supply the first pass voltage as a voltage higher than the second pass voltage while applying the program voltage to the selected word line. ### Claim 8 (depends on 1) The semiconductor memory device according to claim 1, wherein the voltage supply circuit is configured to apply a second voltage to a selected auxiliary word line disposed at a substantially same level as the selected word line among the plurality of auxiliary word lines while applying the read voltage to the selected word line. ### Claim 9 (depends on 8) The semiconductor memory device according to claim 8, wherein the voltage supply circuit is configured to supply at least one of: a ground voltage and a negative voltage, as the second voltage, while applying the read voltage to the selected word line. ### Claim 10 (depends on 8) The semiconductor memory device according to claim 8, wherein the voltage supply circuit is configured to: apply a second pass voltage to the selected word line before applying the read voltage to the selected word line, and supply at least one of: a ground voltage and a positive voltage less than the second pass voltage, as the first voltage, while applying the read voltage to the selected word line. ### Claim 11 (depends on 8) The semiconductor memory device according to claim 8, wherein the voltage supply circuit is configured to: apply a second pass voltage to the selected word line before applying the read voltage to the selected word line, and supply the first pass voltage as a voltage higher than the second pass voltage while applying the read voltage to the selected word line. ### Claim 12 A semiconductor memory device, comprising: a channel layer comprising a first side portion and a second side portion, the first and second side portions facing different directions; a gate stacked body enclosing the first side portion of the channel layer; an auxiliary gate stacked body enclosing the second side portion of the channel layer; and a data storage layer disposed between the first side portion of the channel layer and the gate stacked body, the data storage layer being formed such that the second side portion of the channel layer is opened. ### Claim 13 (depends on 12) The semiconductor memory device according to claim 12, further comprising: a doped semiconductor structure overlapping the gate stacked body and the auxiliary gate stacked body; and a bit line overlapping the doped semiconductor structure with the gate stacked body and the auxiliary gate stacked body interposed between the bit line and the doped semiconductor structure, wherein the first side portion and the second side portion of the channel layer are coupled to the bit line and the doped semiconductor structure. ### Claim 14 (depends on 13) The semiconductor memory device according to claim 13, wherein: the gate stacked body comprises a plurality of word lines spaced apart from each other between the doped semiconductor structure and the bit line, and the auxiliary gate stacked body includes a plurality of auxiliary word lines spaced apart from each other between the doped semiconductor structure and the bit line. ### Claim 15 (depends on 14) The semiconductor memory device according to claim 14, wherein the plurality of auxiliary word lines are disposed at substantially same levels as the plurality of word lines and spaced apart from the plurality of word lines. ### Claim 16 (depends on 12) The semiconductor memory device according to claim 12, further comprising: a tunnel insulating layer disposed between the first side portion of the channel layer and the data storage layer and extending to a space between the second side portion of the channel layer and the auxiliary gate stacked body; and a blocking insulating layer disposed between the data storage layer and the gate stacked body and extending to a space between the auxiliary gate stacked body and the tunnel insulating layer. ### Claim 17 (depends on 16) The semiconductor memory device according to claim 16, further comprising: an insulating structure disposed between the gate stacked body and the auxiliary gate stacked body and being in contact with the blocking insulating layer.