# US 12,224,012 B2 · All level coarse/fine programming of memory cells > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,012 B2 - Document ID: US12224012B2 - Status: Granted - Kind: B2 - Application number: 18/127,768 - Filed: 2023-03-29 - Published: 2023-10-05 - Granted: 2025-02-11 - Earliest claimed: 2022-04-05 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Lawrence Celso Miranda; Tomoko Ogura Iwasaki; Sheyang Ning; Jeffrey S. McNeil - Web page: https://patentgrep.com/patent/US12224012B2 ## CPC - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/10: Programming or data input circuits - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/24: Bit-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 2211/5621: Multilevel programming verification - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Described are systems and methods for all level coarse/fine programming of memory cells. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and a set of target bitlines; causing a first voltage to be applied to the target wordline, wherein the first voltage is incremented every time period over a number of time periods that corresponds to a number of threshold voltages to be programmed; causing a second voltage to be applied to a first bitline over the number of time periods; causing a third voltage to be applied to a second bitline, wherein the third voltage is incremented during a second time period of the number of time periods, wherein the second time period follows a first time period; causing a fourth voltage to be applied to a third bitline, wherein the fourth voltage is incremented during a third time period of the number of time periods, wherein the third time period follows the second time period; and causing a fifth voltage to be applied to a fourth bitline over the number of time periods. ## Claims ### Claim 1 A system, comprising: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and a set of target bitlines; causing a first voltage to be applied to the target wordline, wherein the first voltage is incremented every time period over a number of time periods that corresponds to a number of threshold voltages to be programmed; causing a second voltage to be applied to a first bitline over the number of time periods; causing a third voltage to be applied to a second bitline, wherein the third voltage is incremented during a second time period of the number of time periods, wherein the second time period follows a first time period; causing a fourth voltage to be applied to a third bitline, wherein the fourth voltage is incremented during a third time period of the number of time periods, wherein the third time period follows the second time period; and causing a fifth voltage to be applied to a fourth bitline over the number of time periods. ### Claim 2 (depends on 1) The system of claim 1, wherein the operations further comprise: causing a read strobe to be performed with respect to the set of memory cells. ### Claim 3 (depends on 1) The system of claim 1, wherein the first bitline is connected to a subset of memory cells to be programmed to a lowest logical level. ### Claim 4 (depends on 1) The system of claim 1, wherein the second bitline is connected to a subset of memory cells to be programmed to an intermediate lowest logical level. ### Claim 5 (depends on 1) The system of claim 1, wherein the third bitline is connected to a subset of memory cells to be programmed to an intermediate lowest logical level. ### Claim 6 (depends on 1) The system of claim 1, wherein the fourth bitline is connected to a subset of memory cells to be programmed to a highest logical level. ### Claim 7 (depends on 1) The system of claim 1, wherein the operations further comprise: causing a fine programming operation to be performed with respect to the set of memory cells, wherein the fine programming operation comprises one or more programming voltage pulses. ### Claim 8 (depends on 1) The system of claim 1, wherein the operations further comprise: causing a coarse programming operation to be performed with respect to the set of memory cells, wherein the coarse programming operation comprises one or more programming voltage pulses. ### Claim 9 A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a controller managing a memory array comprising a plurality of memory cells, cause the controller to perform operations, comprising: identifying a set of memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and a set of target bitlines; causing a first voltage to be applied to the target wordline, wherein the first voltage is incremented every time period over a number of time periods that corresponds to a number of threshold voltages to be programmed; causing a second voltage to be applied to a first bitline over the number of time periods; causing a third voltage to be applied to a second bitline, wherein the third voltage is incremented during a second time period of the number of time periods, wherein the second time period follows a first time period; causing a fourth voltage to be applied to a third bitline, wherein the fourth voltage is incremented during a third time period of the number of time periods, wherein the third time period follows the second time period; and causing a fifth voltage to be applied to a fourth bitline over the number of time periods. ### Claim 10 (depends on 9) The computer-readable non-transitory storage medium of claim 9, wherein the first bitline is connected to a subset of memory cells to be programmed to a lowest logical level. ### Claim 11 (depends on 9) The computer-readable non-transitory storage medium of claim 9, wherein the second bitline is connected to a subset of memory cells to be programmed to an intermediate lowest logical level. ### Claim 12 (depends on 9) The computer-readable non-transitory storage medium of claim 9, wherein the fourth bitline is connected to a subset of memory cells to be programmed to a highest logical level. ### Claim 13 (depends on 9) The computer-readable non-transitory storage medium of claim 9, wherein the operations further comprise: causing a fine programming operation to be performed with respect to the set of memory cells, wherein the fine programming operation comprises one or more programming voltage pulses. ### Claim 14 (depends on 9) The computer-readable non-transitory storage medium of claim 9, wherein the operations further comprise: causing a coarse programming operation to be performed with respect to the set of memory cells, wherein the coarse programming operation comprises one or more programming voltage pulses. ### Claim 15 A method, comprising: identifying, by a controller managing a memory array comprising a plurality of memory cells, a set of memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and a set of target bitlines; causing a first voltage to be applied to the target wordline, wherein the first voltage is incremented every time period over a number of time periods that corresponds to a number of threshold voltages to be programmed; causing a second voltage to be applied to a first bitline over the number of time periods; causing a third voltage to be applied to a second bitline, wherein the third voltage is incremented during a second time period of the number of time periods, wherein the second time period follows a first time period; causing a fourth voltage to be applied to a third bitline, wherein the fourth voltage is incremented during a third time period of the number of time periods, wherein the third time period follows the second time period; and causing a fifth voltage to be applied to a fourth bitline over the number of time periods. ### Claim 16 (depends on 15) The method of claim 15, further comprising: causing a read strobe to be performed with respect to the set of memory cells. ### Claim 17 (depends on 15) The method of claim 15, wherein the first bitline is connected to a subset of memory cells to be programmed to a lowest logical level. ### Claim 18 (depends on 15) The method of claim 15, wherein the second bitline is connected to a subset of memory cells to be programmed to an intermediate lowest logical level. ### Claim 19 (depends on 15) The method of claim 15, wherein the fourth bitline is connected to a subset of memory cells to be programmed to a highest logical level. ### Claim 20 (depends on 15) The method of claim 15, further comprising: causing a fine programming operation to be performed with respect to the set of memory cells, wherein the fine programming operation comprises one or more programming voltage pulses.