# US 12,224,010 B2 · Non-volatile memory

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- Number: US 12,224,010 B2
- Document ID: US12224010B2
- Status: Granted
- Kind: B2
- Application number: 18/021,606
- Filed: 2021-08-05
- Published: 2023-09-28
- Granted: 2025-02-11
- Earliest claimed: 2020-09-18
- Assignees: Rohm Co., Ltd.
- Applicants: Rohm Co., Ltd.
- Inventors: Seiji Takenaka
- Web page: https://patentgrep.com/patent/US12224010B2

## CPC

- G11C 16/0441: {comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates}
- G11C 16/04: using variable threshold transistors, e.g. FAMOS
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 17/14: in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A non-volatile memory has: a first and a second transistor having their gates connected together; a resistor having a first and a second terminal, with the first terminal connected to the source of the first transistor; a read voltage feed circuit configured to feed a read voltage for turning on at least one of the first and second transistors to between the gate of the first transistor and the second terminal of the resistor and to between the gate and the source of the second transistor; and a signal output circuit configured to output, in a read operation in which the read voltage feed circuit feeds the read voltage, a signal associated with a first or second value based on the drain currents of the first and second transistors.

## Claims

### Claim 1

A non-volatile memory, comprising:
a first transistor;
a second transistor having a gate connected to a gate of the first transistor;
a resistor having a first terminal and a second terminal, the first terminal being connected to a source of the first transistor;
a read voltage feed circuit configured to feed a read voltage for turning on at least one of the first and second transistors to between the gate of the first transistor and the second terminal of the resistor and to between the gate and a source of the second transistor; and
a signal output circuit configured to output, in a read operation in which the read voltage feed circuit feeds the read voltage, a signal associated with a first value or a signal associated with a second value based on drain currents of the first and second transistors.

### Claim 2 (depends on 1)

The non-volatile memory according to claim 1, wherein
in the read operation, the signal output circuit
outputs the signal associated with the first value if the drain current of the second transistor is higher than the drain current of the first transistor and
outputs the signal associated with the second value if the drain current of the first transistor is higher than the drain current of the second transistor.

### Claim 3 (depends on 2)

The non-volatile memory according to claim 2, further comprising a program circuit configured to perform a program operation to increase a gate threshold voltage of the second transistor by injecting hot carriers into the second transistor.

### Claim 4 (depends on 3)

The non-volatile memory according to claim 3, wherein,
in the read operation performed before the program operation, the drain current of the second transistor is higher than the drain current of the first transistor and,
in the read operation performed after the program operation, with the gate threshold voltage of the second transistor having been increased in the program operation, the drain current of the first transistor is higher than the drain current of the second transistor.

### Claim 5 (depends on 3)

The non-volatile memory according to claim 3, wherein
the first and second transistors have a same structure, and
before the program operation, the first and second transistors have a same gate threshold voltage.

### Claim 6

A non-volatile memory, comprising:
a first transistor;
a second transistor having a gate connected to a gate of the first transistor;
a resistor having a first terminal and a second terminal, the first terminal being connected to a source of the first transistor;
a read voltage feed circuit configured to be able to feed a read voltage for turning on at least one of the first and second transistors; and
a signal output circuit configured to be able to output, in a read operation in which the read voltage feed circuit feeds the read voltage, a signal associated with a first value or a signal associated with a second value based on drain currents of the first and second transistors.

### Claim 7 (depends on 6)

The non-volatile memory according to claim 6, wherein
when the read operation is performed, the signal output circuit
can output the signal associated with the first value if the drain current of the second transistor is higher than the drain current of the first transistor and
can output the signal associated with the second value if the drain current of the first transistor is higher than the drain current of the second transistor.

### Claim 8 (depends on 7)

The non-volatile memory according to claim 7, further comprising a program circuit configured to be able to perform a program operation to increase a gate threshold voltage of the second transistor by injecting hot carriers into the second transistor.

### Claim 9 (depends on 8)

The non-volatile memory according to claim 8, wherein,
when the read operation is performed before the program operation, in the read operation, the drain current of the second transistor is higher than the drain current of the first transistor and
when the read operation is performed after the program operation, in the read operation, with the gate threshold voltage of the second transistor having been increased in the program operation, the drain current of the first transistor is higher than the drain current of the second transistor.

### Claim 10 (depends on 8)

The non-volatile memory according to claim 8, wherein
the first and second transistors have a same structure, and
before the program operation, the first and second transistors have a same gate threshold voltage.