# US 12,224,008 B2 · Non-volatile static random access memory

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- Number: US 12,224,008 B2
- Document ID: US12224008B2
- Status: Granted
- Kind: B2
- Application number: 18/087,279
- Filed: 2022-12-22
- Published: 2024-05-23
- Granted: 2025-02-11
- Earliest claimed: 2022-11-21
- Assignees: National Cheng Kung University
- Applicants: National Cheng Kung University
- Inventors: Darsen Duane Lu; Mohammed Aftab Baig; Siao-Shan Huang; Fu Yuan Chang
- Web page: https://patentgrep.com/patent/US12224008B2

## CPC

- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G11C 14/0072: {and the nonvolatile element is a ferroelectric element}
- G06F 3/0613: {in relation to throughput}
- G06F 3/0625: {Power saving in storage systems}
- G06F 3/0629: {Configuration or reconfiguration of storage systems}
- G06F 3/0673: {Single storage device}
- G06N 3/06: Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N 3/063: using electronic means
- G11C 7/16: Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
- G11C 8/16: Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

A non-volatile static random access memory includes: a static random access memory, a reading element and a first embedded non-volatile memory. The static random access memory includes a first inverter, a second inverter and two transistors, an output terminal of the first inverter and the input terminal of the second inverter are electrically connected to each other to serve as a Q node, an input terminal of the first inverter and an output terminal of the second inverter are electrically connected to each other to serve as a QB node, and the two transistors are electrically connected to the Q node and the QB node, respectively. The reading element is electrically connected to the Q node. The first embedded non-volatile memory is electrically connected to the QB node.

## Claims

### Claim 1

A non-volatile static random access memory, comprising:
a static random access memory comprising a first inverter, a second inverter and two transistors, an output terminal of the first inverter and an input terminal of the second inverter are electrically connected to each other to serve as a Q node, an input terminal of the first inverter and an output terminal of the second inverter are electrically connected to each other to serve as a QB node, and the two transistors are electrically connected to the Q node and the QB node, respectively;
a reading element electrically connected to the Q node, wherein the reading element comprises a first reading transistor and a second reading transistor, a gate electrode of the first reading transistor is electrically connected to the Q node, a source electrode of the second reading transistor is electrically connected to a drain electrode of the first reading transistor, a gate electrode of the second reading transistor is electrically connected to a read word line, and a drain electrode of the second reading transistor is electrically connected to a read bit line; and
a first embedded non-volatile memory electrically connected to the QB node.

### Claim 2 (depends on 1)

The non-volatile static random access memory according to claim 1, further comprising a second embedded non-volatile memory electrically connected to the Q node.

### Claim 3 (depends on 2)

The non-volatile static random access memory according to claim 2, further comprising:
a first control transistor electrically connected to the first embedded non-volatile memory and the QB node, and disposed between the first embedded non-volatile memory and the QB node; and
a second control transistor electrically connected to the second embedded non-volatile memory and the Q node, and disposed between the second embedded non-volatile memory and the Q node.

### Claim 4

A non-volatile static random access memory, comprising:
a static random access memory comprising a first inverter, a second inverter and two transistors, an output terminal of the first inverter and an input terminal of the second inverter are electrically connected to each other to serve as a Q node, an input terminal of the first inverter and an output terminal of the second inverter are electrically connected to each other to serve as a QB node, and the two transistors are electrically connected to the Q node and the QB node, respectively;
a reading element electrically connected to the Q node, wherein the reading element comprises a first reading transistor, the first reading transistor comprises a gate electrode, a source electrode and a drain electrode, the gate electrode is electrically connected to the Q node, the source electrode is electrically connected to a read word line, and the source electrode is electrically connected to a read bit line; and
a first embedded non-volatile memory electrically connected to the QB node.

### Claim 5 (depends on 1)

The non-volatile static random access memory according to claim 1, wherein the reading element is a first reading element, the read word line is a first read word line, the read bit line is a first read bit line, and the non-volatile static random access memory further comprises a second reading element, wherein the second reading element comprises a third reading transistor and a fourth reading transistor, a gate electrode of the third reading transistor is electrically connected to the QB node, a source electrode of the fourth reading transistor is electrically connected to a drain electrode of the third reading transistor, a gate electrode of the fourth reading transistor is electrically connected to a second read word line, and a drain electrode of the fourth reading transistor is electrically connected to a second read bit line.

### Claim 6 (depends on 1)

The non-volatile static random access memory according to claim 1, wherein the first embedded non-volatile memory is electrically connected to the QB node through a control transistor.