# US 12,223,997 B2 · Nonvolatile semiconductor memory device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,223,997 B2
- Document ID: US12223997B2
- Status: Granted
- Kind: B2
- Application number: 18/490,148
- Filed: 2023-10-19
- Published: 2024-02-08
- Granted: 2025-02-11
- Earliest claimed: 2019-08-28
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Toshifumi Watanabe; Naofumi Abiko
- Web page: https://patentgrep.com/patent/US12223997B2

## CPC

- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- G11C 11/4094: Bit-line management or control circuits
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/32: Timing circuits
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 11/1072: {in multilevel memories}
- G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 11/5671: {using charge trapping in an insulator}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 2211/563: Multilevel memory reading aspects
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.

## Claims

### Claim 1

A semiconductor memory device comprising:
a memory cell;
a word line connected to a gate of the memory cell;
a bit line connected to the memory cell;
a first transistor connected to the bit line; and
a control circuit configured to perform a read operation on the memory cell,
wherein the control circuit is configured to, during the read operation,
apply to the word line a first voltage, then a second voltage greater than the first voltage at a first timing, and then a third voltage smaller than the second voltage at a second timing after the first timing, and
apply to a gate of the first transistor a fourth voltage, then a fifth voltage at a third timing after the first timing and before the second timing, and then a sixth voltage that is higher than the fourth voltage and lower than the fifth voltage at a fourth timing after the second timing.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein the third voltage is a read voltage.

### Claim 3 (depends on 1)

The semiconductor memory device according to claim 1, wherein the second voltage is a read pass voltage.

### Claim 4 (depends on 1)

The semiconductor memory device according to claim 1, further comprising:
a source line connected to the memory cell,
wherein the control circuit is configured to, during the read operation, apply to the source line a seventh voltage, then an eighth voltage greater than the seventh voltage, then a ninth voltage smaller than the eighth voltage at a fifth timing after the first timing, and then a tenth voltage greater than the ninth voltage at a sixth timing after the fifth timing, the third voltage being applied to the word line at the sixth timing.

### Claim 5 (depends on 4)

The semiconductor memory device according to claim 4, wherein the fifth timing is after the third timing.

### Claim 6 (depends on 4)

The semiconductor memory device according to claim 4, wherein the sixth timing is after the second timing.

### Claim 7 (depends on 1)

The semiconductor memory device according to claim 1, further comprising:
a source line connected to the memory cell,
wherein the control circuit is configured to, during the read operation, apply to the source line a seventh voltage, then an eighth voltage greater than the seventh voltage, then a ninth voltage smaller than the eighth voltage at a fifth timing after the first timing, and then a tenth voltage greater than the ninth voltage at a sixth timing after the fifth timing, the sixth voltage being applied to the gate of the first transistor at the sixth timing.

### Claim 8 (depends on 7)

The semiconductor memory device according to claim 7, wherein the fifth timing is after the third timing.

### Claim 9 (depends on 7)

The semiconductor memory device according to claim 7, wherein the sixth timing is after the second timing.

### Claim 10 (depends on 1)

The semiconductor memory device according to claim 1, further comprising:
a source line connected to the memory cell; and
a source line driver connected to the source line,
wherein the source line driver is configured to apply to the source line four or more voltages.

### Claim 11 (depends on 1)

The semiconductor memory device according to claim 1, further comprising:
a source line connected to the memory cell; and
a source line driver connected to the source line,
wherein the control circuit is configured to, during the read operation, apply to the source line a seventh voltage, then an eighth voltage greater than the seventh voltage, then a ninth voltage smaller than the eighth voltage at a fifth timing after the first timing, and then a tenth voltage greater than the ninth voltage at a sixth timing after the fifth timing, and
wherein the source line driver is configured to apply to the source line four or more voltages including the seventh voltage, the eighth voltage, the ninth voltage and the tenth voltage.

### Claim 12 (depends on 1)

The semiconductor memory device according to claim 1, further comprising:
a source line connected to the memory cell,
wherein the source line is connected to a node at a voltage that is set according to a reference voltage, and the reference voltage is decreased at the fifth timing and increased at the sixth timing.

### Claim 13 (depends on 12)

The semiconductor memory device according to claim 12, wherein the reference voltage is maintained constant between the fifth timing and the sixth timing.

### Claim 14 (depends on 12)

The semiconductor memory device according to claim 12, wherein the reference voltage is varied between the fifth timing and the sixth timing.

### Claim 15 (depends on 14)

The semiconductor memory device according to claim 14, wherein the reference voltage is decreased between the fifth timing and the sixth timing.

### Claim 16 (depends on 1)

The semiconductor memory device according to claim 1, wherein the second voltage is higher than read voltages.

### Claim 17 (depends on 1)

The semiconductor memory device according to claim 1, further comprising:
a source line connected to the memory cell,
wherein the control circuit is configured to, during the read operation, apply to the source line a seventh voltage, and an eighth voltage greater than the seventh voltage.