# US 12,223,993 B2 · Content addressable memory based on selfrectifying ferroelectric tunnel junction element

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- Number: US 12,223,993 B2
- Document ID: US12223993B2
- Status: Granted
- Kind: B2
- Application number: 17/933,093
- Filed: 2022-09-17
- Published: 2023-03-23
- Granted: 2025-02-11
- Earliest claimed: 2021-09-17
- Assignees: Industry-Academic Cooperation Foundation, Yonsei University
- Applicants: Industry-Academic Cooperation Foundation, Yonsei University
- Inventors: Seong Ook Jung; Se Hee Lim
- Web page: https://patentgrep.com/patent/US12223993B2

## CPC

- G11C 11/2275: {Writing or programming circuits or methods}
- G11C 15/046: {using non-volatile storage elements}
- G11C 11/22: using ferroelectric elements
- G11C 11/2255: {Bit-line or column circuits}
- G11C 11/2297: {Power supply circuits}
- G11C 15/04: using semiconductor elements
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A content addressable memory based on a self-rectifying ferroelectric tunnel junction element comprises: a cell array unit having a plurality of TCAM cells, each comprising two self-rectifying ferroelectric tunnel junction elements (SR-FTJ) connected between a corresponding match line of a plurality of match lines extending in a first direction and a corresponding bit line pair of a plurality of bit line pairs extending in a second direction; a precharge unit precharging a corresponding match line of the plurality of match lines to a power supply voltage level in response to a precharge signal; and a data input/output unit having a plurality of access transistor pairs electrically connecting or disconnecting a corresponding bit line pair among the plurality of bit line pairs and a source line, in response to a voltage applied through a corresponding search line pair among a plurality of search line pairs according to data to be written or searched.

## Claims

### Claim 1

A ternary content addressable memory (TCAM) comprising:
a cell array unit having a plurality of TCAM cells, each comprising two self-rectifying ferroelectric tunnel junction elements (hereinafter, SR-FTJ) connected between a corresponding match line of a plurality of match lines extending in a first direction and a corresponding bit line pair of a plurality of bit line pairs extending in a second direction intersecting the first direction;
a precharge unit precharging a corresponding match line of the plurality of match lines to a power supply voltage level in response to a precharge signal; and
a data input/output unit having a plurality of access transistor pairs electrically connecting or disconnecting a corresponding bit line pair among the plurality of bit line pairs and a source line, in response to a voltage applied through a corresponding search line pair among a plurality of search line pairs according to data to be written or searched.

### Claim 2 (depends on 1)

The TCAM according to claim 1,
wherein each of the plurality of TCAM cells includes:
a first SR-FTJ connected between a corresponding match line and a bit line bar of a corresponding bit line pair; and
a second SR-FTJ connected between a corresponding match line and a bit line of a corresponding bit line pair.

### Claim 3 (depends on 2)

The TCAM according to claim 2,
wherein in each of the plurality of TCAM cells,
when data “0” is stored by a write operation, the first SR-FTJ has a low resistance state (LRS) and the second SR-FTJ has a high resistance state (HRS), and
when data “1” is stored, the first SR-FTJ has a high resistance state and the second SR-FTJ has a low resistance state, and
when data “X” (don't care) is stored, both the first and second FeFETs have a high resistance state.

### Claim 4 (depends on 3)

The TCAM according to claim 3,
wherein each of the plurality of access transistor pairs includes:
a first access transistor connected between a bit line bar of a corresponding bit line pair and the source line and having a gate connected with a search line of a corresponding search line pair; and
a second access transistor connected between a bit line of a corresponding bit line pair and the source line and having a gate connected with a search line bar of a corresponding search line pair.

### Claim 5 (depends on 4)

The TCAM according to claim 4,
wherein in a 1st phase of a write operation divided into the 1st phase and a 2nd phase, the TCAM selects a match line corresponding to an address applied together with data and applies a voltage of −VW/2 based on a write voltage (VW), and applies a ground voltage to unselected match lines, and applies a voltage of VW/2 to the source line, so that the first SR-FTJ or the second SR-FTJ of the TCAM cell corresponding to the selected match among the plurality of TCAM cells has a high resistance state according to a voltage level applied through a corresponding search line pair.

### Claim 6 (depends on 5)

The TCAM according to claim 5,
wherein in the TCAM,
when a ground voltage and a voltage of VW/2 are respectively applied to a search line and a search line bar of a corresponding search line pair among the plurality of search line pairs, the second SR-FTJ of a corresponding TCAM cell of a plurality of TCAM cells connected to the selected match line has a high resistance state,
when a voltage of VW/2 and a ground voltage are respectively applied to the search line and the search line bar of a corresponding search line pair, the first SR-FTJ of the corresponding TCAM cell connected to the selected match line has a high resistance state, and
when a voltage of VW/2 is applied to each of the search line and the search line bar of a corresponding search line pair, the first SR-FTJ of the corresponding TCAM cell connected to the selected match line has a high resistance state.

### Claim 7 (depends on 6)

The TCAM according to claim 6,
wherein in the 2nd phase of the write operation, the TCAM applies a voltage of VW/2 to the selected match line, a ground voltage to unselected match lines, and a voltage of −VW/2 to the source line, so that the first SR-FTJ or the second SR-FTJ of the TCAM cell corresponding to the selected match among the plurality of TCAM cells has a low resistance state according to a voltage level applied through a corresponding search line pair.

### Claim 8 (depends on 7)

The TCAM according to claim 7,
wherein in the TCAM,
when a ground voltage and a voltage of −VW/2 are respectively applied to the search line and the search line bar of a corresponding search line pair, the first SR-FTJ of a corresponding TCAM cell of a plurality of TCAM cells connected to the selected match line has a low resistance state, and
when a voltage of −VW/2 and a ground voltage are respectively applied to the search line and the search line bar of a corresponding search line pair, the second SR-FTJ of the corresponding TCAM cell connected to the selected match line has a low resistance state.

### Claim 9 (depends on 8)

The TCAM according to claim 8,
wherein to the first and second SR-FTJs of the plurality of TCAM cells,
in the 1st phase of the write operation, a ground voltage is applied as a body voltage, and in the 2nd phase, a voltage of −VW/2 is applied.

### Claim 10 (depends on 8)

The TCAM according to claim 8,
wherein the precharge unit includes a plurality of precharge transistors connected between a power supply voltage and a corresponding match line of the plurality of match lines and receiving the precharge signal through gates.

### Claim 11 (depends on 10)

The TCAM according to claim 10,
wherein each of the plurality of precharge transistors, in a precharge phase of a search operation, which is divided into the precharge phase and an evaluation phase, is turned on in response to the precharge signal activated to a ground voltage level to precharge a corresponding match line among the plurality of match lines to a power supply voltage level, and in the write operation and the evaluation phase, is turned off in response to the precharge signal deactivated to a power supply voltage level.

### Claim 12 (depends on 11)

The TCAM according to claim 11,
wherein in the precharge phase, the TCAM applies a power supply voltage to the source line and the search line and the search line bar of each of the plurality of search line pairs, thereby precharging bit line bars and bit lines of the plurality of bit line pairs to a power supply voltage level.

### Claim 13 (depends on 12)

The TCAM according to claim 12,
wherein in the evaluation phase, the TCAM applies a ground voltage to the source line, and
when the data to be searched is “0”, the ground voltage and the power supply voltage are applied to the search line and the search line bar, respectively, and
when the data to be searched is “1”, the power supply voltage and the ground voltage are applied to the search line and the search line bar, respectively.