# US 12,223,991 B2 · Semiconductor storage apparatus

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- Number: US 12,223,991 B2
- Document ID: US12223991B2
- Status: Granted
- Kind: B2
- Application number: 17/907,276
- Filed: 2021-04-07
- Published: 2023-04-13
- Granted: 2025-02-11
- Earliest claimed: 2020-04-15
- Assignees: Sony Semiconductor Solutions Corporation
- Applicants: Sony Semiconductor Solutions Corporation
- Inventors: Taro Tatsuno
- Web page: https://patentgrep.com/patent/US12223991B2

## CPC

- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- G11C 11/1655: {Bit-line or column circuits}
- G11C 11/1659: {Cell access}
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10N 50/10: Magnetoresistive devices
- G11C 14/00: Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A semiconductor storage apparatus according to one embodiment of the present disclosure includes a plurality of memory cells and a control circuit. Each of the memory cells includes a magnetization reversal memory device and a first switch device that controls a current to flow to the magnetization reversal memory device. The control circuit performs a writing control based on an asymmetric property of a writing error rate curve line with respect to a writing voltage of the magnetization reversal memory device.

## Claims

### Claim 1

A semiconductor storage apparatus, comprising:
a plurality of memory cells divided into a plurality of groups, wherein
each memory cell of the plurality of memory cells comprises:
a magnetization reversal memory device; and
a first switch device configured to control a current to flow to the magnetization reversal memory device;
a plurality of wiring lines for each group of the plurality of groups, wherein
each wiring line of the plurality of wiring lines is coupled to the first switch device of a corresponding memory cell of the plurality of memory cells;
a plurality of second switch devices for each wiring line of the plurality of wiring lines; and
a control circuit configured to:
perform a writing control, based on an asymmetric property of a writing error rate curve line with respect to a writing voltage of the magnetization reversal memory device, wherein
the writing control is performed with Wa and Wb,
the Wa and the Wb are different based on an ON period of the first switch device,
the Wa is a pulse width upon a write operation of a first state to the magnetization reversal memory device,
the Wb is a pulse width upon a write operation of a second state to the magnetization reversal memory device, and
the plurality of second switch devices is configured to control a supply, to the plurality of wiring lines, of a voltage to use upon the write operation of the second state to the magnetization reversal memory device.

### Claim 2 (depends on 1)

The semiconductor storage apparatus according to claim 1, wherein,
in a case where a pulse upon the write operation of the first state to the magnetization reversal memory device is a first pulse and a pulse upon the write operation of the second state to the magnetization reversal memory device is a second pulse, the control circuit is further configured to:
output the first pulse to the magnetization reversal memory device in a writing period; and
output the second pulse to the magnetization reversal memory device in a blanking period.

### Claim 3 (depends on 2)

The semiconductor storage apparatus according to claim 2, wherein the control circuit is further configured to perform the writing control to cause the Wa to be smaller than the Wb by control of the ON period of the first switch device.

### Claim 4 (depends on 1)

The semiconductor storage apparatus according to claim 1, wherein
the control circuit is further configured to:
divide the plurality of memory cells into the plurality of groups; and
determine a necessity of the write operation of the second state to the each group of the plurality of groups, based on a state of the magnetization reversal memory device included in a single memory cell in the each group of the plurality of groups.

### Claim 5 (depends on 1)

The semiconductor storage apparatus according to claim 1, wherein
each memory cell of the plurality of memory cells includes:
a plurality of magnetization reversal memory devices, wherein the plurality of magnetization reversal memory devices comprises the magnetization reversal memory device; and
a plurality of first switch devices configured to control the current to flow to each magnetization reversal memory device of the plurality of magnetization reversal memory devices, wherein the plurality of first switch devices comprises the first switch device.

### Claim 6 (depends on 5)

The semiconductor storage apparatus according to claim 5, wherein a first magnetization reversal memory device of the plurality of magnetization reversal memory devices is different from a second magnetization reversal memory device of the plurality of magnetization reversal memory devices in data retaining characteristic.

### Claim 7 (depends on 6)

The semiconductor storage apparatus according to claim 6, wherein the first magnetization reversal memory device is different from the second magnetization reversal memory device in at least one a formation material or a size.

### Claim 8 (depends on 7)

The semiconductor storage apparatus according to claim 7, wherein the first magnetization reversal memory device is different from the second magnetization reversal memory device in a height of layers.

### Claim 9 (depends on 1)

The semiconductor storage apparatus according to claim 1, wherein
the plurality of memory cells is divided into a plurality of memory cell arrays, and
a first memory cell array of the plurality of memory cell arrays is configured by specific memory cells that include specific magnetization reversal memory devices in which a data retaining characteristic is different from that of a second memory cell array of the plurality of memory cell arrays.

### Claim 10 (depends on 9)

The semiconductor storage apparatus according to claim 9, wherein
each memory cell of the plurality of memory cells includes:
a plurality of magnetization reversal memory devices, wherein the plurality of magnetization reversal memory devices comprises the magnetization reversal memory device; and
a plurality of first switch devices configured to control the current to flow to each magnetization reversal memory device of the plurality of magnetization reversal memory devices, wherein the plurality of first switch devices comprises the first switch device, and
the plurality of magnetization reversal memory devices included in a same memory cell has a same data retaining characteristic.

### Claim 11 (depends on 9)

The semiconductor storage apparatus according to claim 9, wherein
the plurality of memory cell arrays includes:
the first memory cell array configured to temporarily hold data inputted to the semiconductor storage apparatus; and
the second memory cell array configured to store, in a nonvolatile manner, the data temporarily held in the first memory cell array, and
a second data retaining characteristic of the magnetization reversal memory device included in a memory cell that configures the second memory cell array is higher than a first data retaining characteristic of the magnetization reversal memory device included in a memory cell that configures the first memory cell array.