# US 12,223,989 B2 · Semiconductor device and method for fabricating the same

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- Number: US 12,223,989 B2
- Document ID: US12223989B2
- Status: Granted
- Kind: B2
- Application number: 18/151,994
- Filed: 2023-01-09
- Published: 2023-05-11
- Granted: 2025-02-11
- Earliest claimed: 2020-07-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Harry-Hak-Lay Chuang; Sheng-Huang Huang; Hung-Cho Wang; Sheng-Chang Chen
- Web page: https://patentgrep.com/patent/US12223989B2

## CPC

- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10N 50/01: Manufacture or treatment
- H10N 50/80: Constructional details
- H10B 61/22: {of the field-effect transistor [FET] type}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A method for fabricating a semiconductor device is provided. The method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
first and second memory cells over the substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element;
a first dielectric layer surrounding the first and second memory cells, wherein the first dielectric layer has a void between the first and second memory cells, a bottom of the void has a first edge portion, a second edge portion, and a middle portion between the first and second edge portions, and the middle portion is higher than the first and second edge portions;
a second dielectric layer over the first dielectric layer; and
first and second conductive features in the first and second dielectric layers and respectively connected to the top electrode of the first memory cell and the top electrode of the second memory cell.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the void is an air void.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first dielectric layer has a top surface continuously extending from a sidewall of the first conductive feature to a sidewall of the second conductive feature.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising:
a protective layer surrounding the first and second memory cells, wherein a sidewall of the top electrode of each of the first and second memory cells is in contact with the protective layer.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein a bottom of the first conductive feature and a bottom of the second conductive feature are in contact with the protective layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
first and second spacers, respectively surrounding the first and second memory cells, wherein a top end of the void is lower than top ends of the first and second spacers.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the void tapers upward in a cross-sectional view.

### Claim 8

A semiconductor device, comprising:
a substrate;
first and second memory cells over the substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; and
a dielectric layer surrounding the first and second memory cells, wherein the dielectric layer has a void between the first and second memory cells, a shortest distance between a top end of the void and the first memory cell is greater than a shortest distance between a bottom end of the void and the first memory cell, and a top surface of the dielectric layer has a recessed region directly above the void of the dielectric layer.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising:
a metal-containing compound layer surrounding the first and second memory cells, wherein the metal-containing compound layer spacing the first and second memory cells from the dielectric layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein a portion of the metal-containing compound layer is below a bottom surface of the bottom electrode.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the metal-containing compound layer is in contact with the top electrode.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein the metal-containing compound layer is a metal oxide layer.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein a thickness of the dielectric layer below the void is greater than a thickness of the dielectric layer over the first and second memory cells.

### Claim 14

A semiconductor device, comprising:
a substrate;
first and second memory cells over the substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; and
a dielectric layer surrounding the first and second memory cells, wherein the dielectric layer has first and second inner sidewalls facing each other and between the first and second memory cells, and a top end of the first inner sidewall of the dielectric layer meets a top end of the second inner sidewall of the dielectric layer, and a bottom end of the first inner sidewall of the dielectric layer is spaced apart from a bottom end of the second inner sidewall of the dielectric layer.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the top end of the first inner sidewall of the dielectric layer is higher than a bottom surface of the resistance switching element.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein the bottom end of the first inner sidewall of the dielectric layer is lower than a bottom surface of the resistance switching element.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, wherein the first inner sidewall is between the second inner sidewall and the first memory cell, and the first inner sidewall of the dielectric layer tapers away from the first memory cell.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the second inner sidewall of the dielectric layer tapers away from the second memory cell.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein the dielectric layer has an inner surface connecting the bottom end of the first inner sidewall of the dielectric layer to the bottom end of the second inner sidewall of the dielectric layer, and the inner surface of the dielectric layer is convex upward.

### Claim 20 (depends on 14)

The semiconductor device of claim 14, further comprising:
first and second conductive features in the dielectric layer and respectively connected to the top electrode of the first memory cell and the top electrode of the second memory cell, and the dielectric layer is in contact with sidewalls of the first and second conductive features.