# US 12,223,926 B2 · Data integrated circuit including latch controlled by clock signals and display device including the same

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- Number: US 12,223,926 B2
- Document ID: US12223926B2
- Status: Granted
- Kind: B2
- Application number: 18/050,080
- Filed: 2022-10-27
- Published: 2023-03-09
- Granted: 2025-02-11
- Earliest claimed: 2015-03-09
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Wontae Kim; Sooyeon Kim; Young-Il Ban; Sunkyu Son
- Web page: https://patentgrep.com/patent/US12223926B2

## CPC

- G09G 3/3688: {suitable for active matrices only}
- G09G 3/3611: {Control of matrices with row and column drivers}
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/0223: Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
- G09G 2370/08: Details of image data interface between the display device controller and the data line driver circuit
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

Provided is a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch. At least two of the latch output signals are activated at different time intervals.

## Claims

### Claim 1

A display device comprising:
a display panel comprising a plurality of data lines, a plurality of gate lines and a plurality of pixels;
a data driving circuit configured to output a plurality of data voltages to the plurality of data lines in response to a data control signal;
a gate driving circuit configured to output a plurality of gate signals to the plurality of gate lines in response to a gate control signal; and
a timing controller configured to output the data control signal and the gate control signal,
wherein the data control signal includes a main clock signal and a clock signal,
wherein the data driving circuit comprising a plurality of data integrated circuits, each of the plurality of data integrated circuits comprises:
a shift register configured to receive the clock signal from the timing controller and output a plurality of latch clock signals that are sequentially activated in response to the clock signal;
a latch circuit configured to latch a plurality of image signals from the timing controller in response to the plurality of latch clock signals from the shift register and output a plurality of digital image signals in response to a plurality of latch output signals;
an output circuit configured to convert the plurality of digital image signals to the plurality of data voltages; and
a clock generator configured to receive the main clock signal, divide the main clock signal to generate the plurality of latch output signals and output the plurality of latch output signals,
wherein the latch circuit comprises:
a first latch group configured to receive a first subset of the image signals, a first subset of the latch clock signals and a first latch output signal from among the plurality of latch output signals, latch the first subset of the image signals based on the first subset of the latch clock signals and output a plurality of first digital image signals of the plurality of digital image signals in response to the first latch output signal; and
a second latch group configured to receive a second subset of the image signals, a second subset of the latch clock signals and a second latch output signal from among the plurality of latch output signals, latch the second subset of the image signals based on the second subset of the latch clock signals and output a plurality of second digital image signals of the plurality of digital image signals in response to the second latch output signal among the plurality of latch output signals, and
wherein an active portion of the first latch output signal is not overlapped with an active portion of the second latch output signal.

### Claim 2 (depends on 1)

The display device of claim 1, wherein the latch circuit further comprises a third latch group configured to output a plurality of third digital image signals of the plurality of digital image signals in response to a third latch output signal among the plurality of latch output signals.

### Claim 3 (depends on 2)

The display device of claim 2, wherein the first latch group simultaneously outputs the plurality of first digital image signals in response to the first latch output signal,
wherein the second latch group simultaneously outputs the plurality of second digital image signals in response to the second latch output signal, and
wherein the third latch group simultaneously outputs the plurality of third digital image signals in response to the third latch output signal.

### Claim 4 (depends on 3)

The display device of claim 3, wherein the output circuit converts the plurality of first digital image signals, the plurality of second digital image signals and the plurality of third digital image signals to the plurality of data voltages.

### Claim 5 (depends on 2)

The display device of claim 2, wherein the first latch output signal and the third latch output signal are activated during a first period, respectively.

### Claim 6 (depends on 5)

The display device of claim 5, wherein the second latch output signal is inactivated in the first period and is activated during a second period after the first period.

### Claim 7 (depends on 1)

The display device of claim 1, wherein the timing controller further outputs an output control signal that determines an output order and the clock generator outputs the plurality of latch output signals in response to the output control signal.

### Claim 8 (depends on 1)

The display device of claim 1, wherein the timing controller further outputs a delay signal and the clock generator adjusts a phase difference between the plurality of latch output signals in response to the delay signal.

### Claim 9 (depends on 1)

The display device of claim 1, where the shift register does not provide the image signals to the latch circuit.

### Claim 10 (depends on 1)

The display device of claim 1, wherein the first latch group includes a plurality of latches, the first latch group receives the first latch output signal and a subset of the latch clock signals, each of the latches receive a corresponding one of the latch clock signals among the subset, and the first latch group outputs the plurality of digital image signals together in response to the first latch output signal.

### Claim 11 (depends on 1)

The display device of claim 1, wherein the shift register includes a cascade of flip flops sharing the clock signal in which an output of each of the flip flops is connected to a data input of a next one of the flip flops in the cascade.