# US 12,223,924 B2 · Liquid crystal display device and electronic device including the same

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- Number: US 12,223,924 B2
- Document ID: US12223924B2
- Status: Granted
- Kind: B2
- Application number: 18/433,519
- Filed: 2024-02-06
- Published: 2024-05-30
- Granted: 2025-02-11
- Earliest claimed: 2009-03-26
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Hajime Kimura; Atsushi Umezaki
- Web page: https://patentgrep.com/patent/US12223924B2

## CPC

- G09G 3/3677: {suitable for active matrices only}
- G02F 1/13624: {having more than one switching element per pixel}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/3688: {suitable for active matrices only}
- G09G 3/3696: {Generation of voltages supplied to electrode drivers}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 62/80: characterised by the materials
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- G02F 2202/10: semiconductor
- G09G 3/3674: {Details of drivers for scan electrodes}
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2300/0809: Several active elements per pixel in active matrix panels
- G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/0275: Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit
- G09G 2330/021: Power management, e.g. power saving
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A driver circuit includes a circuit 200, a transistor 101_1, and a transistor 101_2. A signal is selectively input from the circuit 200 to a gate of the transistor 101_1 and the transistor 101_2, so that the transistor 101_1 and the transistor 101_2 are controlled to be on or off. The transistor 101_1 and the transistor 101_2 are turned on or off; thus, the wiring 112 and the wiring 111 become conducting or non-conducting.

## Claims

### Claim 1

A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a capacitor,
wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor comprises a semiconductor layer comprising an oxide semiconductor,
wherein one of a source and a drain of the first transistor is directly connected to a clock signal line,
wherein one of a source and a drain of the second transistor is directly connected to the clock signal line,
wherein one of a source and a drain of the third transistor is directly connected to the clock signal line,
wherein the other of the source and the drain of the first transistor is directly connected to an output signal line,
wherein the other of the source and the drain of the second transistor is directly connected to the output signal line,
wherein the other of the source and the drain of the third transistor is directly connected to the output signal line,
wherein a gate of the first transistor is directly connected to one of a source and a drain of the fourth transistor,
wherein the other of the source and the drain of the fourth transistor is directly connected to one of a source and a drain of the fifth transistor,
wherein the other of the source and the drain of the fifth transistor is directly connected to a signal line,
wherein a first electrode of the capacitor is directly connected to a gate of the first transistor,
wherein a second electrode of the capacitor is directly connected to the output signal line,
wherein, in a period when the fourth transistor and the fifth transistor are each an on-state, the first transistor turns on by inputting a potential of the signal line to the gate of the first transistor through the fourth transistor and the fifth transistor, and
wherein a potential of a gate electrode of the first transistor, a potential of a gate electrode of the second transistor, and a potential of a gate electrode of the third transistor are controlled independently.

### Claim 2

A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a capacitor,
wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor comprises a semiconductor layer comprising an oxide semiconductor,
wherein one of a source and a drain of the first transistor is directly connected to a clock signal line,
wherein one of a source and a drain of the second transistor is directly connected to the clock signal line,
wherein one of a source and a drain of the third transistor is directly connected to the clock signal line,
wherein the other of the source and the drain of the first transistor is directly connected to an output signal line,
wherein the other of the source and the drain of the second transistor is directly connected to the output signal line,
wherein the other of the source and the drain of the third transistor is directly connected to the output signal line,
wherein a gate of the first transistor is directly connected to one of a source and a drain of the fourth transistor,
wherein the other of the source and the drain of the fourth transistor is directly connected to one of a source and a drain of the fifth transistor,
wherein the other of the source and the drain of the fifth transistor is directly connected to a signal line,
wherein a first electrode of the capacitor is directly connected to a gate of the first transistor,
wherein a second electrode of the capacitor is directly connected to the output signal line,
wherein the fourth transistor and the fifth transistor are configured to control a timing of raising a potential of the gate of the first transistor, and
wherein a gate electrode of the first transistor, a gate electrode of the second transistor, and a gate electrode of the third transistor are controlled independently.

### Claim 3

A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a capacitor,
wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor comprises a semiconductor layer comprising an oxide semiconductor,
wherein one of a source and a drain of the first transistor is electrically connected to a clock signal line,
wherein one of a source and a drain of the second transistor is electrically connected to the clock signal line,
wherein one of a source and a drain of the third transistor is electrically connected to the clock signal line,
wherein the other of the source and the drain of the first transistor is electrically connected to an output signal line,
wherein the other of the source and the drain of the second transistor is electrically connected to the output signal line,
wherein the other of the source and the drain of the third transistor is electrically connected to the output signal line,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a signal line,
wherein a first electrode of the capacitor is electrically connected to a gate of the first transistor,
wherein a second electrode of the capacitor is electrically connected to the output signal line,
wherein, in a period when the fourth transistor and the fifth transistor are each an on-state, the first transistor turns on by inputting a potential of the signal line to the gate of the first transistor through the fourth transistor and the fifth transistor, and
wherein a potential of a gate electrode of the first transistor, a potential of a gate electrode of the second transistor, and a potential of a gate electrode of the third transistor are controlled independently.