# US 12,223,923 B2 · Display panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,223,923 B2 - Document ID: US12223923B2 - Status: Granted - Kind: B2 - Application number: 18/408,648 - Filed: 2024-01-10 - Published: 2024-05-02 - Granted: 2025-02-11 - Earliest claimed: 2009-11-26 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Jae-Hoon Lee; Seung-Hwan Moon; Yong-Soon Lee; Young-Su Kim; Chang-Ho Lee; Whee-Won Lee; Jun-Yong Song; Yu-Han Bae - Web page: https://patentgrep.com/patent/US12223923B2 ## CPC - G09G 3/3677: {suitable for active matrices only} - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2330/021: Power management, e.g. power saving - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal. ## Claims ### Claim 1 A display device comprising: a display area including a gate line; a gate driver electrically connected to the gate line, the gate driver including a plurality of stages and being integrated on a substrate, wherein a stage of the plurality of stages comprises: a first transistor including a control electrode electrically connected to a first node, a first electrode electrically connected to a clock signal line, and a second electrode electrically connected to the gate line; a third transistor including a control electrode electrically connected to a second node which is different from the first node, a first electrode electrically connected to a first voff signal line to which a first voff signal is input, and a second electrode electrically connected to the second electrode of the first transistor; an eleventh transistor including a control electrode electrically connected to the second node, a first electrode electrically connected to a second voff signal line, and a second electrode electrically connected to a carry signal out terminal; a seventeenth transistor including a control electrode electrically connected to a second input terminal, a first electrode electrically connected to the second voff signal line, and a second electrode electrically connected to the carry signal out terminal; and a fifteenth transistor including a control electrode electrically connected to the first node, a first electrode, and a second electrode electrically connected to the carry signal out terminal. ### Claim 2 (depends on 1) The display device of claim 1, wherein the stage further comprises: a fifth transistor including a control electrode, a first electrode electrically connected to the second voff signal line, and a second electrode electrically connected to the second node. ### Claim 3 (depends on 2) The display device of claim 2, wherein the stage further comprises: a tenth transistor including a control electrode electrically connected to the second node, a first electrode electrically connected to the second voff signal line, and a second electrode electrically connected to the first node. ### Claim 4 (depends on 3) The display device of claim 3, wherein the stage further comprises: a second transistor including a control electrode, a first electrode, and a second electrode, wherein the first electrode is electrically connected to the first voff signal line, and the second electrode is electrically connected to the second electrode of the first transistor. ### Claim 5 (depends on 4) The display device of claim 4, wherein the stage further comprises: a sixth transistor including a control electrode, a first electrode electrically connected to the second voff signal line, and a second electrode electrically connected to the first node. ### Claim 6 (depends on 5) The display device of claim 5, wherein the stage further comprises: a ninth transistor including a control electrode, a first electrode electrically connected to the second voff signal line, and a second electrode electrically connected to the first node. ### Claim 7 (depends on 6) The display device of claim 6, wherein the control electrode of the ninth transistor is electrically connected to the second input terminal. ### Claim 8 (depends on 6) The display device of claim 6, wherein the stage further comprises: a fourth transistor including a control electrode, a first electrode and a second electrode, wherein the control electrode and the first electrode are electrically connected to each other, and the second electrode is electrically connected to the first node. ### Claim 9 (depends on 1) The display device of claim 1, wherein a voltage level of the first voff signal is different from a voltage level of the second voff signal. ### Claim 10 (depends on 9) The display device of claim 9, wherein the voltage level of the first voff signal is higher than the voltage level of the second voff signal.