# US 12,223,916 B2 · Data driving circuit and a display device including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,223,916 B2 - Document ID: US12223916B2 - Status: Granted - Kind: B2 - Application number: 18/096,057 - Filed: 2023-01-12 - Published: 2023-10-12 - Granted: 2025-02-11 - Earliest claimed: 2022-04-12 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Subin Kim - Web page: https://patentgrep.com/patent/US12223916B2 ## CPC - G09G 3/3275: Details of drivers for data electrodes - G09G 2310/0289: Details of voltage level shifters arranged for use in a driving circuit - G09G 2310/0294: Details of sampling or holding circuits arranged for use in a driver for data electrodes - G09G 2320/0223: Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes - G09G 2320/0276: for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction - G09G 2320/04: Maintaining the quality of display appearance - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A data driving circuit including: a latch which receives an output image signal and outputs a latch data signal including a plurality of bits; a transition detector which compares the latch data signal of a current line with the latch data signal of a previous line, and outputs a first transition detection signal based on the comparison; a delay compensator which outputs a delay data signal obtained by delaying some of the plurality of bits of the latch data signal based on the first transition detection signal; a level shifter which outputs a level shift data signal obtained by changing a voltage level of the delay data signal; and an output circuit which converts the level shift data signal into a data signal and provides the data signal obtained by converting the level shift data signal to a data line. ## Claims ### Claim 1 A data driving circuit, comprising: a latch which receives an output image signal and outputs a latch data signal including a plurality of bits; a transition detector which compares the latch data signal of a current line with the latch data signal of a previous line, and outputs a first transition detection signal based on the comparison; a delay compensator which outputs a delay data signal obtained by delaying some of the plurality of bits of the latch data signal based on the first transition detection signal; a level shifter which outputs a level shift data signal obtained by changing a voltage level of the delay data signal; and an output circuit which converts the level shift data signal into a data signal and provides the data signal obtained by converting the level shift data signal to a data line, wherein the delay compensator includes: a counter which counts a number of the first transition detection signal having a first value in the current line, and outputs a first count signal based on the counted number; a delay controller which outputs a control signal when the first count signal is greater than a first reference value; and a delay circuit which outputs the delay data signal obtained by delaying some of the plurality of bits of the latch data signal in response to the control signal. ### Claim 2 (depends on 1) The data driving circuit of claim 1, wherein the transition detector outputs the first transition detection signal as the first value when the latch data signal of the current line and the latch data signal of the previous line correspond to a first pattern. ### Claim 3 (depends on 2) The data driving circuit of claim 2, wherein the first pattern is a pattern in which a most significant bit of the latch data signal of the previous line is a first bit value, each of remaining lower bits except for the most significant bit of the latch data signal of the previous line is a second bit value, a most significant bit of the latch data signal of the current line is the second bit value, and each of remaining lower bits except for the most significant bit of the latch data signal of the current line is the first bit value. ### Claim 4 (depends on 1) The data driving circuit of claim 1, wherein the delay circuit outputs the delay data signal by delaying some of lower bits of the plurality of bits of the latch data signal in response to the control signal. ### Claim 5 (depends on 4) The data driving circuit of claim 4, wherein the delay circuit outputs the delay data signal by delaying a most significant bit of the plurality of bits of the latch data signal in response to the control signal. ### Claim 6 (depends on 4) The data driving circuit of claim 4, wherein the delay circuit outputs the delay data signal by delaying remaining bits except for a most significant bit of the plurality of bits of the latch data signal in response to the control signal. ### Claim 7 A data driving circuit, comprising: a latch which receives an output image signal and outputs a latch data signal including a plurality of bits; a transition detector which compares the latch data signal of a current line with the latch data signal of a previous line, and outputs a first transition detection signal based on the comparison; a delay compensator which outputs a delay data signal obtained by delaying some of the plurality of bits of the latch data signal based on the first transition detection signal; a level shifter which outputs a level shift data signal obtained by changing a voltage level of the delay data signal; and an output circuit which converts the level shift data signal into a data signal and provides the data signal obtained by converting the level shift data signal to a data line, wherein the delay compensator includes: a counter which counts a number of the first transition detection signal having a first value in the current line to output a first count signal, and counts a number of a second transition detection signal having the first value to output a second count signal; a delay controller which outputs a control signal based on a difference value between the first count signal and the second count signal; and a delay circuit which outputs the delay data signal obtained by delaying some of the plurality of bits of the latch data signal in response to the control signal. ### Claim 8 (depends on 7) The data driving circuit of claim 7, wherein the transition detector: outputs the first transition detection signal as the first value when the latch data signal of the current line and the latch data signal of the previous line correspond to a first pattern, and outputs a second transition detection signal as the first value when the latch data signal of the current line and the latch data signal of the previous line correspond to a second pattern. ### Claim 9 (depends on 7) The data driving circuit of claim 7, wherein the delay controller outputs the control signal such that some of the plurality of bits of the latch data signal are delayed when an absolute value of the difference value is greater than a reference value. ### Claim 10 (depends on 9) The data driving circuit of claim 9, wherein the delay circuit outputs the delay data signal by delaying remaining bits except for a most significant bit of the plurality of bits of the latch data signal in response to the control signal. ### Claim 11 (depends on 9) The data driving circuit of claim 9, wherein the delay circuit outputs the delay data signal by delaying a most significant bit of the plurality of bits of the latch data signal in response to the control signal. ### Claim 12 A data driving circuit, comprising: a latch which receives an output image signal and outputs a latch data signal including a plurality of bits; a transition detector which outputs a first transition detection signal of a first value when the latch data signal of a current line and the latch data signal of a previous line correspond to a first pattern, and outputs a second transition detection signal of the first value when the latch data signal of the current line and the latch data signal of the previous line correspond to a worst pattern; a delay compensator which outputs a delay data signal obtained by delaying some of the plurality of bits of the latch data signal based on a difference value between a number of the first transition detection signal having the first value in the current line and a number of the second transition detection signal having the first value in the current line; a level shifter which outputs a level shift data signal obtained by changing a voltage level of the delay data signal; and an output circuit which converts the level shift data signal into a data signal and provides the data signal obtained by converting the level shift data signal to a data line. ### Claim 13 (depends on 12) The data driving circuit of claim 12, wherein the delay compensator includes: a counter which counts a number of the first transition detection signal having the first value in the current line to output a first count signal, and counts a number of the second transition detection signal having the first value to output a second count signal; a delay controller which outputs a control signal when an absolute value of a difference value between the first count signal and the second count signal is greater than a reference value; and a delay circuit which outputs the delay data signal obtained by delaying some of the plurality of bits of the latch data signal in response to the control signal. ### Claim 14 A data driving circuit, comprising: a latch which receives an image signal and outputs a latch data signal including a plurality of bits; a transition detector which compares the latch data signal of a current line with the latch data signal of a previous line, and outputs a first transition detection signal based on the comparison, wherein the first transition detection signal has a first value when the latch data signal of the current line and the latch data signal of the previous line correspond to a predetermined pattern; a delay compensator which outputs a delay data signal obtained by delaying some of the plurality of bits of the latch data signal based on the first transition detection signal; a level shifter which outputs a level shift data signal obtained by changing a voltage level of the delay data signal; and an output circuit which converts the level shift data signal into a data signal and provides the data signal obtained by converting the level shift data signal to a data line, wherein the predetermined pattern is a pattern in which a most significant bit of the latch data signal of the previous line is a first bit value, each of remaining lower bits except for the most significant bit of the latch data signal of the previous line is a second bit value, a most significant bit of the latch data signal of the current line is the second bit value, and each of remaining lower bits except for the most significant bit of the latch data signal of the current line is the first bit value. ### Claim 15 (depends on 14) The data driving circuit of claim 14, wherein the first bit value is 0 and the second bit value is 1.