# US 12,223,904 B2 · Semiconductor device and method for driving semiconductor device

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- Number: US 12,223,904 B2
- Document ID: US12223904B2
- Status: Granted
- Kind: B2
- Application number: 18/569,779
- Filed: 2022-06-23
- Published: 2024-09-26
- Granted: 2025-02-11
- Earliest claimed: 2021-06-30
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Yuki Okamoto; Tatsuya Onuki; Hidetomo Kobayashi; Munehiro Kozuma; Takanori Matsuzaki; Susumu Kawashima; Yutaka Okazaki
- Web page: https://patentgrep.com/patent/US12223904B2

## CPC

- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09F 9/30: in which the desired character or characters are formed by combining individual elements (panels comprising a number of electrodes in a single cell controlling light arriving from an independent light source, e.g. electro-optical or magneto-optical cell, G02F1/00)
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- H05B 33/02: Details
- H05B 33/12: Light sources with substantially two-dimensional [2D] radiating surfaces
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D 84/0126: {the components including insulated gates, e.g. IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2300/0852: being a dynamic memory with more than one capacitor
- G09G 2330/021: Power management, e.g. power saving
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G09F: DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- H05B: ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The invention of the application is the invention regarding a semiconductor device and a method for driving the semiconductor device. The semiconductor device includes first and second transistors, first to fifth switches, first to third capacitors, and a display element. The first transistor (M2) comprises a back gate, a gate of the first transistor is electrically connected to the first switch (M1), the second switch (M3) and the first capacitor (C1) are positioned between the gate of the first transistor and a source of the first transistor, the back gate of the first transistor is electrically connected to the third switch (M4), the second capacitor (C2) is positioned between the back gate of the first transistor and the source of the first transistor, the source of the first transistor is electrically connected to the fourth switch (M6) and a drain of the second transistor (M5), a gate of the second transistor is electrically connected to the fifth switch (M7), the third capacitor (C3) is positioned between the gate of the second transistor and a source of the second transistor, and the source of the second transistor is electrically connected to the display element (61).

## Claims

### Claim 1

A semiconductor device comprising:
first and second transistors, first to fifth switches, first to third capacitors, and a display element,
wherein the first transistor comprises a back gate,
wherein a gate of the first transistor is electrically connected to the first switch,
wherein the second switch and the first capacitor are positioned between the gate of the first transistor and a source of the first transistor,
wherein the back gate of the first transistor is electrically connected to the third switch,
wherein the second capacitor is positioned between the back gate of the first transistor and the source of the first transistor,
wherein the source of the first transistor is electrically connected to the fourth switch and a drain of the second transistor,
wherein a gate of the second transistor is electrically connected to the fifth switch,
wherein the third capacitor is positioned between the gate of the second transistor and a source of the second transistor, and
wherein the source of the second transistor is electrically connected to the display element.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the first switch is provided between a first wiring and the gate of the first transistor,
wherein the second switch is provided between the gate of the first transistor and the source of the first transistor,
wherein the third switch is provided between a second wiring and the back gate of the first transistor,
wherein the fourth switch is provided between a third wiring and the source of the first transistor, and
wherein the fifth switch is provided between a fourth wiring and the gate of the second transistor.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1,
wherein each of the first to fifth switches is a transistor.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1,
wherein at least one of the first transistor and the second transistor comprises a metal oxide in a semiconductor layer where a channel is formed.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4,
wherein the metal oxide comprises at least one of indium and zinc.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1,
wherein the display element comprises an organic EL element having a tandem structure.

### Claim 7

A method for driving a semiconductor device comprising first and second transistors, first to fifth switches, first to third capacitors, and a display element,
wherein the first transistor comprises a back gate,
wherein a gate of the first transistor is electrically connected to the first switch,
wherein the second switch and the first capacitor are positioned between the gate of the first transistor and a source of the first transistor,
wherein the back gate of the first transistor is electrically connected to the third switch,
wherein the second capacitor is positioned between the back gate of the first transistor and the source of the first transistor,
wherein the source of the first transistor is electrically connected to the fourth switch and a drain of the second transistor,
wherein a gate of the second transistor is electrically connected to the fifth switch,
wherein the third capacitor is positioned between the gate of the second transistor and a source of the second transistor, and
wherein the source of the second transistor is electrically connected to the display element, the method comprising:
first to fourth processings,
wherein in the first processing, a first potential is supplied to the source of the first transistor through the fourth switch and supplied to the gate of the first transistor through the second switch and a second potential higher than the first potential is supplied to the back gate of the first transistor through the third switch,
wherein in the second processing, a third potential is supplied to the gate of the first transistor through the first switch and the first potential is supplied to the source of the first transistor through the fourth switch,
wherein in the third processing, a potential that brings the second transistor into a conduction state is supplied to the gate of the second transistor through the fifth switch, and
wherein in the fourth processing, a potential that brings the second transistor into a non-conduction state is supplied to the gate of the second transistor through the fifth switch.

### Claim 8 (depends on 7)

The method for driving the semiconductor device according to claim 7,
wherein the first switch is configured to establish or break electrical continuity between a first wiring and the gate of the first transistor,
wherein the second switch is configured to establish or break electrical continuity between the gate of the first transistor and the source of the first transistor,
wherein the third switch is configured to establish or break electrical continuity between a second wiring and the back gate of the first transistor,
wherein the fourth switch is configured to establish or break electrical continuity between a third wiring and the source of the first transistor, and
wherein the fifth switch is configured to establish or break electrical continuity between a fourth wiring and the gate of the second transistor.

### Claim 9 (depends on 7)

The method for driving the semiconductor device according to claim 7,
wherein each of the first to fifth switches is a transistor.

### Claim 10 (depends on 7)

The method for driving the semiconductor device according to claim 7,
wherein at least one of the first transistor and the second transistor comprises a metal oxide in a semiconductor layer where a channel is formed.

### Claim 11 (depends on 10)

The method for driving the semiconductor device according to claim 10,
wherein the metal oxide comprises at least one of indium and zinc.

### Claim 12 (depends on 7)

The method for driving the semiconductor device according to claim 7,
wherein the display element comprises an organic EL element having a tandem structure.

### Claim 13 (depends on 7)

The method for driving the semiconductor device according to claim 7,
wherein the first processing starts after the fourth processing starts,
wherein the third processing starts after the fourth processing is finished,
wherein the first processing is finished before the third processing starts,
wherein the second processing starts after the first processing is finished, and
wherein the fourth processing starts after the second processing is finished and after the third processing is finished.

### Claim 14

A method for driving a semiconductor device comprising a transistor, a switch, and a signal line,
wherein a source of the transistor is electrically connected to one terminal of the switch, the method comprising:
first to fourth processings,
wherein in the first processing, a first potential is supplied to the source of the transistor and a gate of the transistor,
wherein in the second processing, the first potential is supplied to the source of the transistor and a potential of the signal line is supplied to the gate of the transistor,
wherein in the third processing, the switch is brought into a conduction state,
wherein in the fourth processing, the switch is brought into a non-conduction state,
wherein the potential of the signal line and the first potential are compared after the fourth processing starts,
wherein in the case where the potential of the signal line and the first potential are the same potential, processing of:
starting the first processing;
finishing the first processing before the third processing starts, and
starting the second processing after the first processing is finished, is performed,
wherein in the case where the potential of the signal line and the first potential are not the same potential, processing of starting the second processing is performed,
wherein the third processing starts after the fourth processing is finished, and
wherein the fourth processing starts after the second processing is finished and after the third processing is finished.