# US 12,223,893 B2 · Display substrate and preparation method thereof, and display apparatus

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- Number: US 12,223,893 B2
- Document ID: US12223893B2
- Status: Granted
- Kind: B2
- Application number: 17/764,993
- Filed: 2021-05-28
- Published: 2023-06-22
- Granted: 2025-02-11
- Earliest claimed: 2021-01-27
- Assignees: Boe Technology Group Co., Ltd.
- Applicants: BOE Technology Group Co., Ltd.
- Inventors: Can Zheng; Li Wang; Long Han; Jianchao Zhu; Libin Liu
- Web page: https://patentgrep.com/patent/US12223893B2

## CPC

- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- H10K 59/1201: {Manufacture or treatment}
- H10K 59/1213: {the pixel elements being TFTs}
- H10K 59/1216: {the pixel elements being capacitors}
- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- H10K 59/353: {characterised by the geometrical arrangement of the RGB subpixels}
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2300/043: Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2300/0852: being a dynamic memory with more than one capacitor
- G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage
- G09G 2310/0297: Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/0242: Compensation of deficiencies in the appearance of colours
- G09G 2320/0257: Reduction of after-image effects
- G09G 2320/045: Compensation of drifts in the characteristics of light emitting or modulating elements
- G09G 2330/021: Power management, e.g. power saving
- G09G 2340/0435: Change or adaptation of the frame rate of the video stream
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

Disclosed are a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a substrate and a plurality of sub-pixels, at least one sub-pixel includes a pixel drive circuit and a light emitting device connected to the pixel drive circuit, the pixel drive circuit includes a plurality of transistors, wherein at least one transistor includes an active layer and two gate electrodes. The substrate is provided with a semiconductor layer and a plurality of conductive layers disposed on one side of the semiconductor layer away from the substrate, at least one conductive layer is provided with at least one electrode plate, and there is an overlapping region between an orthographic projection of the electrode plate on the substrate and an orthographic projection of the active layer between the two gate electrodes on the substrate.

## Claims

### Claim 1

A display substrate, comprising:
a substrate and a plurality of sub-pixels, wherein at least one sub-pixel comprises a pixel drive circuit and a light emitting device connected to the pixel drive circuit, the pixel drive circuit comprises a plurality of transistors, at least one transistor comprises an active layer and two gate electrodes; the substrate is provided with a semiconductor layer and a plurality of conductive layers disposed on a side of the semiconductor layer away from the substrate, at least one conductive layer is provided with at least one electrode plate, and there is an overlapping region between an orthographic projection of the electrode plate on the substrate and an orthographic projection of the active layer between the two gate electrodes on the substrate.

### Claim 2 (depends on 1)

The display substrate according to claim 1, wherein the plurality of conductive layers comprise a first conductive layer, a second conductive layer, and a third conductive layer disposed sequentially on a side of the semiconductor layer away from the substrate, and the electrode plate is disposed on the first conductive layer, the second conductive layer, or the third conductive layer.

### Claim 3 (depends on 2)

The display substrate according to claim 2, wherein the display substrate further comprises a first power supply line connected to the pixel drive circuit, and at least one electrode plate is connected to the first power supply line.

### Claim 4 (depends on 2)

The display substrate according to claim 2, wherein the plurality of transistors at least comprise a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor;
a first electrode of the first transistor is connected to a data signal line, and a second electrode of the first transistor is connected to a third node;
a first electrode of the second transistor is connected to a first node, and a second electrode of the second transistor is connected to a fourth node;
a gate electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to a first power supply line, and a second electrode of the third transistor is connected to the fourth node;
a first electrode of the fourth transistor is connected to an initial signal line, and a second electrode of the fourth transistor is connected to the first node; and
a first electrode of the fifth transistor is connected to the first power supply line, and a second electrode of the fifth transistor is connected to a second node.

### Claim 5 (depends on 4)

The display substrate according to claim 4, wherein the pixel drive circuit further comprises a storage capacitor and a threshold capacitor, the storage capacitor comprises a first electrode plate and a second electrode plate of the storage capacitor, and the threshold capacitor comprises a first electrode plate and a second electrode plate of the threshold capacitor; the first electrode plate of the storage capacitor is connected to the third node, and the second electrode plate of the storage capacitor is connected to the second node; and the first electrode plate of the threshold capacitor is connected to the first node, and the second electrode plate of the threshold capacitor is connected to the second node.

### Claim 6 (depends on 5)

The display substrate according to claim 5, wherein the first electrode plate of the storage capacitor and the first electrode plate of the threshold capacitor are disposed on the first conductive layer, the first electrode plate of the storage capacitor and the first electrode plate of the threshold capacitor are arranged at intervals, and the first electrode plate of the storage capacitor is not overlapped with the semiconductor layer.

### Claim 7 (depends on 5)

The display substrate according to claim 5, wherein the second electrode plate of the storage capacitor and the second electrode plate of the threshold capacitor are disposed on the second conductive layer and are connected to each other, there is an overlapping region between an orthographic projection of the second electrode plate of the storage capacitor on the substrate and an orthographic projection of the first electrode plate of the storage capacitor on the substrate, and there is an overlapping region between an orthographic projection of the second electrode plate of the threshold capacitor on the substrate and an orthographic projection of the first electrode plate of the threshold capacitor on the substrate.

### Claim 8 (depends on 4)

The display substrate according to claim 4, wherein the fifth transistor is a double-gate transistor, and the fifth transistor at least comprises a fifth active layer and two fifth gate electrodes; the electrode plate comprises a first electrode plate, and there is an overlapping region between an orthographic projection of the first electrode plate on the substrate and an orthographic projection of the fifth active layer located between the two fifth gate electrodes on the substrate.

### Claim 9 (depends on 8)

The display substrate according to claim 8, wherein the two fifth gate electrodes are disposed on the first conductive layer, the first electrode plate is disposed on the first conductive layer or the second conductive layer, and the first power supply line is disposed on the third conductive layer, wherein the first power supply line is connected to the first electrode plate through a via hole.

### Claim 10 (depends on 9)

The display substrate according to claim 9, wherein the second conductive layer further comprises a first power connection line, the first electrode plate is connected to the first power connection line, and the first power supply line is connected to the first power connection line through a via hole.

### Claim 11 (depends on 4)

The display substrate according to claim 4, wherein the second transistor is a double-gate transistor, and the second transistor at least comprises a second active layer and two second gate electrodes; the electrode plate comprises a second electrode plate, and there is an overlapping region between an orthographic projection of the second electrode plate on the substrate and an orthographic projection of the second active layer located between the two second gate electrodes on the substrate.

### Claim 12 (depends on 11)

The display substrate according to claim 11, wherein the two second gate electrodes are disposed on the first conductive layer, the second electrode plate is disposed on the first conductive layer or the second conductive layer, the third conductive layer is further provided with a first connection electrode, and the first connection electrode is connected to the second electrode plate through a via hole.

### Claim 13 (depends on 12)

The display substrate according to claim 12, wherein the first connection electrode is used as a second electrode of the first transistor and is connected to the first electrode plate of the storage capacitor through a via hole.

### Claim 14 (depends on 12)

The display substrate according to claim 12, wherein the fourth transistor is a double-gate transistor, and the fourth transistor at least comprises a fourth active layer and two fourth gate electrodes; and there is an overlapping region between an orthographic projection of the first connection electrode on the first power supply line and an orthographic projection of the fourth active layer located between the two fourth gate electrodes on the first power supply line.

### Claim 15 (depends on 4)

The display substrate according to claim 4, wherein the third conductive layer is further provided with a second connection electrode, the second connection electrode is simultaneously used as the first electrode of the second transistor and the second electrode of the fourth transistor, and the second connection electrode is connected to the first electrode plate of the threshold capacitor through a via hole.

### Claim 16 (depends on 4)

The display substrate according to claim 4, wherein the third conductive layer is further provided with a third connection electrode, the third connection electrode is used as the first electrode of the fourth transistor and is connected to the initial signal line through a via hole, and there is an overlapping region between an orthographic projection of the third connection electrode on the substrate and an orthographic projection of a fourth active layer between two gate electrodes of the fourth transistor on the substrate.

### Claim 17 (depends on 1)

A display apparatus, comprising the display substrate according to claim 1.

### Claim 18

A preparation method for a display substrate, wherein the display substrate comprises a substrate and a plurality of sub-pixels, at least one sub-pixel comprises a pixel drive circuit and a light emitting device connected to the pixel drive circuit, the pixel drive circuit comprises a plurality of transistors, and at least one transistor comprises an active layer and two gate electrodes; the preparation method comprises:
forming a semiconductor layer on the substrate and a plurality of conductive layers disposed on a side of the semiconductor layer away from the substrate, wherein at least one conductive layer is provided with at least one electrode plate, and there is an overlapping region between an orthographic projection of the electrode plate on the substrate and an orthographic projection of the active layer between the two gate electrodes on the substrate.

### Claim 19 (depends on 18)

The preparation method for the display substrate according to claim 18, wherein forming the semiconductor layer on the substrate and the plurality of conductive layers disposed on the side of the semiconductor layer away from the substrate comprises:
forming a semiconductor layer on the substrate; and
sequentially forming a first conductive layer, a second conductive layer, and a third conductive layer on the semiconductor layer, wherein the electrode plate is located on the first conductive layer, the second conductive layer, or the third conductive layer.

### Claim 20 (depends on 19)

The preparation method for the display substrate according to claim 19, wherein at least one conductive layer is provided with a first power supply line connected to the pixel drive circuit, and at least one electrode plate is connected to the first power supply line.