# US 12,223,881 B2 · Gate driver and display device including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,223,881 B2 - Document ID: US12223881B2 - Status: Granted - Kind: B2 - Application number: 18/497,875 - Filed: 2023-10-30 - Published: 2024-08-01 - Granted: 2025-02-11 - Earliest claimed: 2023-01-31 - Assignees: LG Display Co., Ltd. - Applicants: LG Display Co., Ltd. - Inventors: Ju Hong Kim; Yong Chan Park - Web page: https://patentgrep.com/patent/US12223881B2 ## CPC - G09G 3/30: using electroluminescent panels - G09G 3/3677: {suitable for active matrices only} - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A gate driver according to an embodiment and a display device including the same are disclosed. The gate driver according to the embodiment includes an output clock line through which an output clock signal is applied, a dummy clock line disposed side by side with the output clock line and through which a dummy clock signal is applied, a pull-up transistor including a first electrode connected to the output clock line, a gate electrode connected to a first control node, and a second electrode connected to an output node from which a gate signal is output, and a pull-down transistor including a first electrode connected to the output node, a gate electrode connected to a second control node, and a second electrode connected to a power line through which a low-potential power voltage is applied. ## Claims ### Claim 1 A gate driver comprising: an output clock line through which an output clock signal is applied; a dummy clock line disposed adjacent to the output clock line and through which a dummy clock signal is applied; a pull-up transistor including a first electrode connected to the output clock line, a gate electrode connected to a first control node, and a second electrode connected to an output node from which a gate signal is output; and a pull-down transistor including a first electrode connected to the output node, a gate electrode connected to a second control node, and a second electrode connected to a power line through which a low-potential power voltage is applied, wherein the output clock line and the dummy clock line are disposed on different layers from each other, wherein the output clock line is disposed on a first layer, wherein the dummy clock line is disposed on a second layer located below the first layer; and wherein the pull-up transistor and the pull-down transistor are disposed on a third layer located below the second layer. ### Claim 2 (depends on 1) The gate driver of claim 1, wherein the output clock line and the dummy clock line are disposed to overlap each other. ### Claim 3 (depends on 1) The gate driver of claim 1, wherein the output clock signal and the dummy clock signal are input in synchronization with each other. ### Claim 4 (depends on 1) The gate driver of claim 1, wherein the output clock signal and the dummy clock signal are a same signal. ### Claim 5 A display device comprising: a data driver configured to output a data voltage; a gate driver including a circuit unit configured to output a gate signal to an output node by transmitting an output clock signal and a low-potential power voltage to the output node according to voltages of a first control node and a second control node; and a plurality of pixel circuits configured to reproduce an input image by receiving the data voltage and the gate signal, wherein the gate driver includes: an output clock line through which the output clock signal is applied; a dummy clock line disposed adjacent to the output clock line and through which a dummy clock signal is applied; a pull-up transistor including a first electrode connected to the output clock line, a gate electrode connected to the first control node, and a second electrode connected to the output node from which the gate signal is output; and a pull-down transistor including a first electrode connected to the output node, a gate electrode connected to the second control node, and a second electrode connected to a power line through which the low-potential power voltage is applied, wherein the output clock signal and the dummy clock signal are a same signal. ### Claim 6 (depends on 5) The display device of claim 5, wherein the output clock line and the dummy clock line are disposed on different layers from each other. ### Claim 7 (depends on 6) The display device of claim 6, wherein the output clock line and the dummy clock line are disposed to overlap each other. ### Claim 8 (depends on 5) The display device of claim 5, wherein the output clock line is disposed on a first layer, and the dummy clock line is disposed on a second layer located below the first layer. ### Claim 9 (depends on 8) The display device of claim 8, wherein the pull-up transistor and the pull-down transistor are disposed on a third layer located below the second layer. ### Claim 10 (depends on 5) The display device of claim 5, wherein the output clock signal and the dummy clock signal are input in synchronization with each other. ### Claim 11 (depends on 5) The display device of claim 5, wherein the gate driver includes a plurality of gate drivers configured to output different gate signals from each other, wherein each of the plurality of gate drivers includes a layer on which the output clock line is positioned and a layer on which the dummy clock line is positioned. ### Claim 12 (depends on 5) The display device of claim 5, wherein the gate driver includes a plurality of gate drivers configured to output different gate signals from each other, wherein each of the plurality of gate drivers includes a layer on which the output clock line is positioned and a layer on which the dummy clock line is positioned, wherein the layer on which the dummy clock line is positioned is integrated into a single layer. ### Claim 13 A gate driver comprising: an output clock line through which an output clock signal is applied; a dummy clock line disposed adjacent to the output clock line and through which a dummy clock signal is applied; a pull-up transistor including a first electrode connected to the output clock line, a gate electrode connected to a first control node, and a second electrode connected to an output node from which a gate signal is output; and a pull-down transistor including a first electrode connected to the output node, a gate electrode connected to a second control node, and a second electrode connected to a power line through which a low-potential power voltage is applied, wherein the output clock signal and the dummy clock signal are a same signal. ### Claim 14 (depends on 13) The gate driver of claim 13, wherein the output clock line and the dummy clock line are disposed on different layers from each other. ### Claim 15 (depends on 14) The gate driver of claim 14, wherein the output clock line and the dummy clock line are disposed to overlap each other. ### Claim 16 (depends on 14) The gate driver of claim 14, wherein the output clock line is disposed on a first layer, and the dummy clock line is disposed on a second layer located below the first layer. ### Claim 17 (depends on 16) The gate driver of claim 16, wherein the pull-up transistor and the pull-down transistor are disposed on a third layer located below the second layer. ### Claim 18 (depends on 13) The gate driver of claim 13, wherein the output clock signal and the dummy clock signal are input in synchronization with each other.