# US 12,223,572 B2 · Separately processing regions or objects of interest from a render engine to a display engine or a display panel

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- Number: US 12,223,572 B2
- Document ID: US12223572B2
- Status: Granted
- Kind: B2
- Application number: 18/299,748
- Filed: 2023-04-13
- Published: 2023-09-07
- Granted: 2025-02-11
- Earliest claimed: 2017-04-24
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Joydeep Ray
- Web page: https://patentgrep.com/patent/US12223572B2

## CPC

- G06F 3/1438: {using more than one graphics controller}
- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06T 7/254: involving subtraction of images
- G06T 11/60: Creating or editing images; Combining images with text
- G06T 15/00: Three-dimensional [3D] image rendering
- G06T 15/005: {General purpose rendering architectures}
- G09G 5/39: Control of the bit-mapped memory
- G06T 2200/28: involving image processing hardware
- G09G 5/001: {Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor}
- G09G 2340/0435: Change or adaptation of the frame rate of the video stream
- G09G 2352/00: Parallel handling of streams of display data
- G09G 2360/06: Use of more than one graphics processor to process data before displaying to one or more screens
- G09G 2360/08: Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs
- G09G 2360/121: using a cache memory
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

Video or graphics, received by a render engine within a graphics processing unit, may be segmented into a region of interest such as foreground and a region of less interest such as background. In other embodiments, an object of interest may be segmented from the rest of the depiction in a case of a video game or graphics processing workload. Each of the segmented portions of a frame may themselves make up a separate surface which is sent separately from the render engine to the display engine of a graphics processing unit. In one embodiment, the display engine combines the two surfaces and sends them over a display link to a display panel. The display controller in the display panel displays the combined frame. The combined frame is stored in a buffer and refreshed periodically. In accordance with another embodiment, video or graphics may be segmented by a render engine into regions of interest or objects of interest and objects not of interest and again each of the separate regions or objects may be transferred to the display engine as a separate surface. Then the display engine may transfer the separate surfaces to a display controller of a display panel over a display link. At the display panel, a separate frame buffer may be used for each of the separate surfaces.

## Claims

### Claim 1

A graphics processing unit, comprising:
a plurality of texture units,
a shared memory coupled to the plurality of texture units,
a plurality of register files coupled to the shared memory,
a plurality of load/store units coupled to the shared memory, and
a plurality of graphics processing cores coupled to the plurality of register files, wherein at least some of the plurality of graphics processing cores are to:
receive a workload prepared by a virtual reality application;
render, in a rendering engine, the workload, comprising to render a plurality of frames, the rendering engine to render at least some of the plurality of frames comprising separate surfaces, including to pixel shade a first region of the at least some of the plurality of frames at a first shading rate and to pixel shade a second region of the at least some of the plurality of frames at a second shading rate that is twice the first shading rate;
provide the plurality of frames to a display engine;
determine whether a display panel is capable of buffering display surfaces separately;
in response to determining that the display panel is not capable of buffering the display surfaces separately, combine the separate surfaces of the at least some of the plurality of frames in the display engine; and
send the plurality of frames to the display panel.

### Claim 2 (depends on 1)

The graphics processing unit of claim 1, further comprising scheduler logic to schedule groups of instructions.

### Claim 3 (depends on 2)

The graphics processing unit of claim 2, further comprising a plurality of arithmetic logic units coupled to the plurality of register files, wherein the plurality of arithmetic logic units are to perform operations on integer data types.

### Claim 4 (depends on 1)

The graphics processing unit of claim 1, wherein the at least some of the plurality of graphics processing cores are to:
receive information to identify a first portion of a first frame based on eye gaze detection;
apply the first shading rate within the first portion of the first frame; and
apply the second shading rate within at least a second portion of the first frame.

### Claim 5 (depends on 1)

The graphics processing unit of claim 1 wherein the graphics processing unit is coupled to a central processing unit, the central processing unit and the graphics processing unit comprising a system on chip.

### Claim 6 (depends on 1)

The graphics processing unit of claim 1, further comprising at least one non-transitory storage medium comprising instructions for execution by the at least some of the plurality of graphics processing units.

### Claim 7

A graphics processor, comprising:
a register file to store information;
a plurality of arithmetic logic units coupled to the register file;
a plurality of texture units coupled to the register file; and
a non-transitory storage medium comprising instructions that when executed cause the graphics processor to:
receive a workload prepared by a virtual reality application;
render the workload, comprising to render a plurality of frames in a rendering engine, the rendering engine to render at least some of the plurality of frames comprising separate surfaces, including to pixel shade a first region of the at least some of the plurality of frames at a first shading rate and to pixel shade a second region of the at least some of the plurality of frames at a second shading rate that is twice the first shading rate;
provide the plurality of frames comprising the separate surfaces to a display engine;
determine whether a display panel is capable of buffering display surfaces separately;
in response to determining that the display panel is not capable of buffering the display surfaces separately, combine the separate surfaces of the at least some of the plurality of frames in the display engine; and
send the plurality of frames to the display panel.

### Claim 8 (depends on 7)

The graphics processor of claim 7, further comprising an interface to communicate with a head-mounted display comprising the display panel.

### Claim 9 (depends on 8)

The graphics processor of claim 8, wherein the graphics processor is to send the plurality of frames comprising the separate surfaces to the display panel when the display panel comprises separate buffers to store the separate surfaces.

### Claim 10 (depends on 8)

The graphics processor of claim 8, wherein the graphics processor is to determine that the head-mounted display comprises separate buffers to store the separate surfaces, prior to sending the plurality of frames comprising the separate surfaces.

### Claim 11 (depends on 7)

The graphics processor of claim 7, wherein the non-transitory storage medium further comprises instructions that when executed cause the graphics processor to, in response to determining that the display panel is capable of buffering the display surfaces separately, separately send the separate surfaces comprising a foreground surface and a background surface.

### Claim 12

A graphics processor, comprising:
a plurality of texture units;
a shared memory coupled to the plurality of texture units;
a plurality of register files coupled to the shared memory;
a plurality of graphics processing cores coupled to the plurality of register files, the plurality of graphics processing cores comprising:
a first portion of the plurality of graphics processing cores to perform floating point operations; and
a second portion of the plurality of graphics processing cores to perform floating point operations and integer operations; and
wherein at least one of the plurality of graphics processing cores is to:
segment at least a portion of a frame into a first surface and a second surface; and
based at least in part on a determination that a display is capable of buffering display surfaces separately, transmit the first surface and the second surface separately to the display.

### Claim 13 (depends on 12)

The graphics processor of claim 12, wherein the at least one graphics processing core is to segment the at least portion of the frame in a render engine.

### Claim 14 (depends on 12)

The graphics processor of claim 12, wherein the at least one graphics processing core is to separately refresh the first surface and the second surface.

### Claim 15 (depends on 14)

The graphics processor of claim 14, wherein the at least one graphics processing core is to separately refresh the first surface at a first rate and the second surface at a second rate, the second rate different than the first rate.

### Claim 16 (depends on 12)

The graphics processor of claim 12, wherein the at least one graphics processing core is to receive information to identify a first portion of the frame, apply a first shading rate within the first portion of the frame, and apply a second shading rate within at least a second portion of the frame.

### Claim 17 (depends on 12)

The graphics processor of claim 12, further comprising at least one special function unit.