# US 12,223,560 B2 · Clock architecture and method supporting PCIE clock, and medium

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- Number: US 12,223,560 B2
- Document ID: US12223560B2
- Status: Granted
- Kind: B2
- Application number: 18/570,597
- Filed: 2022-06-07
- Published: 2024-08-15
- Granted: 2025-02-11
- Earliest claimed: 2021-12-23
- Assignees: Suzhou Metabrain Intelligent Technology Co., Ltd.
- Applicants: Suzhou Metabrain Intelligent Technology Co., Ltd.
- Inventors: Haibo Wang; Zhihua Ge
- Web page: https://patentgrep.com/patent/US12223560B2

## CPC

- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)}
- G06F 13/4291: {using a clocked protocol}
- G06F 2213/0026: PCI express
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A clock architecture supporting a PCIE clock, including a controller, a GPU, a PCIE switch, a FPGA, a first clock generator, a second clock generator, a first clock fan-out device and a second clock fan-out device; the first clock generator is configured to generate a 100 MHz homologous clock signal; the second clock generator is configured to generate a 100 MHz non-homologous clock signal; the FPGA is connected to the PCIE switch and the GPU, and configured to read clock architecture modes supported by the PCIE switch and the GPU, acquire corresponding 100 MHz clock signals according to the clock architecture modes, and fan out the acquired 100 MHz clock signals to the PCIE switch and the GPU to be used, the clock architecture modes are a homologous mode and a non-homologous mode.

## Claims

### Claim 1

A clock architecture supporting a PCIE clock, comprising: a controller, a graphics processing unit (GPU), a programmable communication interface extension (PCIE) switch, a field-programmable gate array (FPGA), a first clock generator, a second clock generator, a first clock fan-out device and a second clock fan-out device;
wherein the first clock generator is connected to the first clock fan-out device, and is configured to generate a 100 MHz homologous clock signal; the first clock fan-out device is connected to the controller and the FPGA, and is configured to fan out the 100 MHz homologous clock signal; and
the second clock generator is connected to the second clock fan-out device, and is configured to generate a 100 MHz non-homologous clock signal; the second clock fan-out device is connected to the FPGA, and is configured to fan out the 100 MHz non-homologous clock signal; the controller is connected to the PCIE switch, the PCIE switch is connected to the GPU;
the FPGA is connected to the PCIE switch and the GPU, and is configured to read clock architecture modes supported by the PCIE switch and the GPU, acquire corresponding 100 MHz clock signals according to the clock architecture modes, and fan out the acquired 100 MHz clock signals to the PCIE switch and the GPU to be used, wherein the clock architecture modes are a homologous mode and a non-homologous mode;
wherein the FPGA is further configured to:
acquire the 100 MHz homologous clock signals when the read clock architecture modes supported by the PCIE switch and the GPU are both the homologous mode;
acquire the 100 MHz non-homologous clock signals when the read clock architecture modes supported by the PCIE switch and the GPU are both the non-homologous mode; and
acquire the 100 MHz homologous clock signal and the 100 MHz non-homologous clock signal when the read clock architecture mode supported by the PCIE switch is the homologous mode and the read clock architecture mode supported by the GPU is the non-homologous mode.

### Claim 2 (depends on 1)

The clock architecture supporting the PCIE clock according to claim 1, further comprising a power supply;
wherein the FPGA is connected to the power supply, and is configured to transmit an enabling signal; and
the power supply is connected to the GPU and the PCIE switch, and is configured to receive the enabling signal to supply power to the GPU and the PCIE switch.

### Claim 3 (depends on 2)

The clock architecture supporting the PCIE clock according to claim 2, wherein the power supply is configured to supply power to the GPU and the PCIE switch through a pin of the GPU or a pin of the PCIE switch.

### Claim 4 (depends on 1)

A method for supporting a PCIE clock, applied to the clock architecture supporting the PCIE clock according to claim 1, comprising:
reading the clock architecture modes supported by the PCIE switch and the GPU, wherein the clock architecture modes are the homologous mode and the non-homologous mode;
acquiring corresponding 100 MHz clock signals according to the clock architecture modes, wherein the 100 MHz clock signals are the 100 MHz homologous clock signal and the 100 MHz non-homologous clock signal; and
transmitting the acquired 100 MHz clock signals correspondingly to the PCIE switch and the GPU to be used;
wherein the acquiring corresponding 100 MHz clock signals according to the clock architecture modes comprises:
acquiring the 100 MHz homologous clock signals when the read clock architecture modes supported by the PCIE switch and the GPU are both the homologous mode;
acquiring the 100 MHz non-homologous clock signals when the read clock architecture modes supported by the PCIE switch and the GPU are both the non-homologous mode; and
acquiring the 100 MHz homologous clock signal and the 100 MHz non-homologous clock signal when the read clock architecture mode supported by the PCIE switch is the homologous mode and the read clock architecture mode supported by the GPU is the non-homologous mode.

### Claim 5 (depends on 4)

The method for supporting the PCIE clock according to claim 4, wherein the reading the clock architecture modes supported by the PCIE switch and the GPU comprises:
reading the clock architecture modes supported by the PCIE switch and the GPU via a system management bus (SMBUS) link.

### Claim 6 (depends on 4)

The method for supporting the PCIE clock according to claim 4, further comprising:
performing a test on testing signals for the 100 MHz homologous clock signal and the 100 MHz non-homologous clock signal after acquiring a loopback board; and
performing, according to a phase difference obtained from the testing signals and practical signals, compensation to suppress the phase difference, wherein the practical signals are the 100 MHz clock signals actually transmitted to the PCIE switch and the GPU.

### Claim 7 (depends on 6)

The method for supporting the PCIE clock according to claim 6, wherein the phase difference comprises both deterministic jitter and random jitter.

### Claim 8 (depends on 7)

The method for supporting the PCIE clock according to claim 7, wherein the phase difference is compensated according to a correction algorithm of the harmonic analysis method in the form of windowing.

### Claim 9 (depends on 4)

The method for supporting the PCIE clock according to claim 4, wherein the reading the clock architecture modes supported by the PCIE switch and the GPU comprises:
reading the clock architecture modes supported by the PCIE switch and the GPU when the PCIE switch and the GPU are powered on successfully.

### Claim 10 (depends on 4)

The method for supporting the PCIE clock according to claim 4, wherein the controller is connected to the PCIE switch, the PCIE switch is connected to the GPU, and data communication between the controller and the PCIE switch as well as between the PCIE switch and the GPU is achieved through a PCIE link.

### Claim 11 (depends on 4)

The method for supporting the PCIE clock according to claim 4, wherein the power supply is configured to supply power to the GPU and the PCIE switch through a pin of the GPU or a pin of the PCIE switch.

### Claim 12 (depends on 1)

The clock architecture supporting the PCIE clock according to claim 1, wherein the FPGA is further configured to:
read the clock architecture modes supported by the PCIE switch and the GPU via a system management bus (SMBUS) link.

### Claim 13 (depends on 1)

The clock architecture supporting the PCIE clock according to claim 1, wherein the controller is connected to the PCIE switch, the PCIE switch is connected to the GPU, and data communication between the controller and the PCIE switch as well as between the PCIE switch and the GPU is achieved through a PCIE link.

### Claim 14

A clock architecture supporting a PCIE clock, comprising a memory and one or more processors, wherein the memory is stored with computer-readable instructions that, when executed by the one or more processors, cause the one or more processors to implement operations of:
reading clock architecture modes supported by a programmable communication interface extension (PCIE) switch and a graphics processing unit (GPU), wherein the clock architecture modes are a homologous mode and a non-homologous mode;
acquiring corresponding 100 MHz clock signals according to the clock architecture modes, wherein the 100 MHz clock signals are the 100 MHz homologous clock signal and the 100 MHz non-homologous clock signal; and
transmitting the acquired 100 MHz clock signals correspondingly to the PCIE switch and the GPU to be used;
wherein the one or more processors is further configured to implement operations of:
acquiring the 100 MHz homologous clock signals when the read clock architecture modes supported by the PCIE switch and the GPU are both the homologous mode;
acquiring the 100 MHz non-homologous clock signals when the read clock architecture modes supported by the PCIE switch and the GPU are both the non-homologous mode; and
acquiring the 100 MHz homologous clock signal and the 100 MHz non-homologous clock signal when the read clock architecture mode supported by the PCIE switch is the homologous mode and the read clock architecture mode supported by the GPU is the non-homologous mode.

### Claim 15 (depends on 14)

The clock architecture supporting a PCIE clock according to claim 14, wherein the one or more processors is further configured to implement operations of:
reading the clock architecture modes supported by the PCIE switch and the GPU via a system management bus (SMBUS) link.

### Claim 16 (depends on 14)

The clock architecture supporting a PCIE clock according to claim 14, wherein the one or more processors is further configured to implement operations of:
performing a test on testing signals for the 100 MHz homologous clock signal and the 100 MHz non-homologous clock signal after acquiring a loopback board; and
performing, according to a phase difference obtained from the testing signals and practical signals, compensation to suppress the phase difference, wherein the practical signals are the 100 MHz clock signals actually transmitted to the PCIE switch and the GPU.

### Claim 17

A non-transitory computer-readable storage medium storing computer-readable instructions, wherein the computer-readable instructions, when executed by one or more processors, cause the one or more processors to implement operations of:
reading clock architecture modes supported by a programmable communication interface extension (PCIE) switch and a graphics processing unit (GPU), wherein the clock architecture modes are a homologous mode and a non-homologous mode;
acquiring corresponding 100 MHz clock signals according to the clock architecture modes, wherein the 100 MHz clock signals are the 100 MHz homologous clock signal and the 100 MHz non-homologous clock signal; and
transmitting the acquired 100 MHz clock signals correspondingly to the PCIE switch and the GPU to be used;
wherein the one or more processors is further configured to implement operations of:
acquiring the 100 MHz homologous clock signals when the read clock architecture modes supported by the PCIE switch and the GPU are both the homologous mode;
acquiring the 100 MHz non-homologous clock signals when the read clock architecture modes supported by the PCIE switch and the GPU are both the non-homologous mode; and
acquiring the 100 MHz homologous clock signal and the 100 MHz non-homologous clock signal when the read clock architecture mode supported by the PCIE switch is the homologous mode and the read clock architecture mode supported by the GPU is the non-homologous mode.