# US 12,223,328 B2 · Generating and executing a control flow > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,223,328 B2 - Document ID: US12223328B2 - Status: Granted - Kind: B2 - Application number: 18/448,079 - Filed: 2023-08-10 - Published: 2024-02-01 - Granted: 2025-02-11 - Earliest claimed: 2015-01-07 - Applicants: Lodestar Licensing Group, LLC - Inventors: Kyle B. Wheeler; Richard C. Murphy; Troy A. Manning; Dean A. Klein - Web page: https://patentgrep.com/patent/US12223328B2 ## CPC - G06F 9/3877: {using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12)} - G06F 9/30: Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) - G06F 9/3004: {to perform operations on memory} - G06F 9/3005: {to perform operations for flow control} - G06F 15/7821: {Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory} - G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} - G11C 7/065: {Differential amplifiers of latching type} - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 7/1036: {using data shift registers} - G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array. ## Claims ### Claim 1 A processor in memory (PIM) apparatus comprising: a memory device configured to receive a first plurality of mathematical operations of first control flow instructions and a second plurality of mathematical operations of second control flow instructions generated by a host, including: a first array of memory cells; a second array of memory cells; a first execution unit, coupled to the first array, to execute the first control flow instructions; a second execution unit, coupled to the second array, to execute the second control flow instructions; a first controller configured to control an execution of the first control flow instructions on data stored in the first array using the first execution unit; and a second controller configured to control an execution of the second control flow instructions on data stored in the second array using the second execution unit. ### Claim 2 (depends on 1) The PIM apparatus of claim 1, wherein the first plurality of mathematical operations and the second plurality of mathematical operations include instructions for manipulating data using the first execution unit and the second execution unit. ### Claim 3 (depends on 1) The PIM apparatus of claim 1, wherein the first plurality of mathematical operations and the second plurality of mathematical operations include logical operations. ### Claim 4 (depends on 3) The PIM apparatus of claim 3, wherein the logical operations include Boolean logical operations. ### Claim 5 (depends on 1) The PIM apparatus of claim 1, wherein the first control flow instructions and the second control flow instructions include compare operations and swap operations. ### Claim 6 (depends on 1) The PIM apparatus of claim 1, wherein the first control flow instructions and the second control flow instructions include Single Instruction Multiple Data (SIMD) operations. ### Claim 7 (depends on 1) The PIM apparatus of claim 1, wherein the first control flow instructions and the second control flow instructions comprise a control flow generated by the memory device. ### Claim 8 (depends on 7) The PIM apparatus of claim 7, wherein the control flow includes an order in which the first control flow instructions and the second control flow instructions are executed. ### Claim 9 (depends on 7) The PIM apparatus of claim 7, wherein the first control flow instructions are associated with a first portion of the control flow and the second control flow instructions are associated with a second portion of the control flow. ### Claim 10 (depends on 7) The PIM apparatus of claim 7, wherein the second control flow instructions are generated by the host while the first execution unit executes the first control flow instructions. ### Claim 11 A system for operating a process in memory (PIM) apparatus comprising: a host, configured to convert host operable instructions into op-code instructions to generate control flow instructions comprising a plurality of mathematical operations; and a memory device, including: an array of memory cells; an execution unit, coupled to the array, to execute the control flow instructions; and a controller configured to control an execution of the control flow instructions on data stored in the array. ### Claim 12 (depends on 11) The system of claim 11, wherein the host is further configured to fetch instructions from the memory device. ### Claim 13 (depends on 12) The system of claim 12, wherein the host is further configured to store the fetched instructions in a cache. ### Claim 14 (depends on 13) The system of claim 13, wherein the host is further configured to decode the fetched instructions stored in the cache. ### Claim 15 (depends on 14) The system of claim 14, wherein the host is further configured to determine the plurality of mathematical operations to be performed based on the op-code associated with the fetched instructions. ### Claim 16 A system for operating a process in memory (PIM) apparatus comprising: a host configured to: decode host operable instructions; and dynamically generate memory operable instructions from the decoded host operable instructions; and a memory device, including: an array of memory cells; an execution unit, coupled to the array, to execute the memory operable instructions; and a controller configured to control an execution of the memory operable instructions on data stored in the array. ### Claim 17 (depends on 16) The system of claim 16, wherein the host is further configured to dynamically generate the memory operable instructions after a program that includes the host operable instructions is compiled. ### Claim 18 (depends on 17) The system of claim 17, wherein the host is further configured to dynamically generate the memory operable instructions associated with a control flow. ### Claim 19 (depends on 18) The system of claim 18, wherein the host is further configured to dynamically generate the control flow for the program. ### Claim 20 (depends on 19) They system of claim 19, wherein the host is further configured to evaluate the decoded host operable instructions to dynamically generate the memory operable instructions.