# US 12,223,327 B2 · CPUs with capture queues to save and restore intermediate results and out-of-order results

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- Number: US 12,223,327 B2
- Document ID: US12223327B2
- Status: Granted
- Kind: B2
- Application number: 18/487,186
- Filed: 2023-10-16
- Published: 2024-02-01
- Granted: 2025-02-11
- Earliest claimed: 2018-12-29
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Timothy D. Anderson; Duc Bui; Joseph Zbiciak; Reid E. Tatge
- Web page: https://patentgrep.com/patent/US12223327B2

## CPC

- G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
- G06F 9/3867: {using instruction pipelines}
- G06F 9/3838: {Dependency mechanisms, e.g. register scoreboarding}
- G06F 9/3863: {using multiple copies of the architectural state, e.g. shadow registers}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

## Claims

### Claim 1

A device comprising:
a processor that includes:
a functional unit configured to execute a first instruction, a second instruction that is subsequent to the first instruction, and a third instruction, wherein the functional unit includes a first pipe stage configured to provide a result of the second instruction and an intermediate result of the third instruction;
a capture queue that includes a first memory coupled to the first pipe stage, wherein the first memory is configured to store the result of the second instruction and the intermediate result of the third instruction; and
a circuit coupled to the functional unit and to the capture queue and that is configured to:
determine that the first instruction and the second instruction both write to a memory location, and that the first pipe stage will produce the result of the second instruction for writing to the memory location prior to completion of the first instruction; and
based on the determination:
cause the result of the second instruction to be provided by the first pipe stage and stored in the first memory; and
after completion of the first instruction, cause the result of the second instruction to be provided by the first memory and stored in the memory location.

### Claim 2 (depends on 1)

The device of claim 1, wherein:
the circuit is configured to cause the functional unit to begin execution of the third instruction after the result of the second instruction is stored in the first memory and before the result of the second instruction is provided by the first memory and stored in the memory location.

### Claim 3 (depends on 1)

The device of claim 1, wherein:
the functional unit includes a second pipe stage; and
the capture queue includes a second memory coupled to the second pipe stage.

### Claim 4 (depends on 1)

The device of claim 1, wherein:
the circuit is configured to:
detect a hazard associated with the third instruction; and
based on the hazard:
cause the intermediate result of the third instruction to be provided by the first pipe stage and stored in the first memory; and
after completion of a fourth instruction, cause the intermediate result of the third instruction to be provided by the first memory to a second pipe stage of the functional unit.

### Claim 5 (depends on 4)

The device of claim 4, wherein the circuit is configured to track a lifetime tracking value for the third instruction based on a number of cycles to complete the third instruction.

### Claim 6 (depends on 5)

The device of claim 5, wherein the circuit is configured to cause the intermediate result of the third instruction to be provided to the second pipe stage based on the lifetime tracking value.

### Claim 7 (depends on 5)

The device of claim 5, wherein the circuit is configured to, based on the hazard, cause the lifetime tracking value to be stored in the first memory.

### Claim 8 (depends on 4)

The device of claim 4, wherein the hazard is based on the third instruction reading a value to be written by the fourth instruction.

### Claim 9 (depends on 1)

The device of claim 1, wherein:
the processor includes a register; and
the memory location is associated with the register.

### Claim 10

A device comprising:
a processor that includes:
a first functional unit configured to execute a first instruction;
a second functional unit configured to execute a second instruction that is subsequent to the first instruction and to execute a third instruction, wherein the second functional unit includes a first pipe stage that is configured to produce a result of the second instruction and an intermediate result of the third instruction;
a capture queue that includes:
a first set of memories coupled to the first functional unit; and
a second set of memories coupled to the second functional unit, wherein the second set of memories includes a first memory coupled to the first pipe stage, wherein the first memory is configured to store the result of the second instruction and the intermediate result of the third instruction; and
a circuit coupled to the first functional unit, the second functional unit, and the capture queue and that is configured to:
determine that the first instruction and the second instruction both write to a memory location, and that the first pipe stage will produce the result of the second instruction for writing to the memory location prior to completion of the first instruction; and
based on the determination:
cause the result of the second instruction to be provided by the first pipe stage and stored in the first memory; and
after completion of the first instruction, cause the result of the second instruction to be provided by the first memory and stored in the memory location.

### Claim 11 (depends on 10)

The device of claim 10, wherein:
the circuit is configured to cause the second functional unit to begin execution of the third instruction after the result of the second instruction is stored in the first memory and before the result of the second instruction is provided by the first memory and stored in the memory location.

### Claim 12 (depends on 10)

The device of claim 10, wherein:
the second functional unit includes a second pipe stage; and
the second set of memories includes a second memory coupled to the second pipe stage.

### Claim 13 (depends on 10)

The device of claim 10, wherein:
the circuit is configured to:
detect a hazard associated with the third instruction; and
based on the hazard:
cause the intermediate result of the third instruction to be provided by the first pipe stage and stored in the first memory; and
after completion of a fourth instruction, cause the intermediate result of the third instruction to be provided by the first memory to a second pipe stage of the second functional unit.

### Claim 14 (depends on 13)

The device of claim 13, wherein the circuit is configured to track a lifetime tracking value for the third instruction based on a number of cycles to complete the third instruction.

### Claim 15 (depends on 14)

The device of claim 14, wherein the circuit is configured to cause the intermediate result of the third instruction to be provided to the second pipe stage based on the lifetime tracking value.

### Claim 16 (depends on 14)

The device of claim 14, wherein the circuit is configured to, based on the hazard, cause the lifetime tracking value to be stored in the first memory.

### Claim 17 (depends on 13)

The device of claim 13, wherein the hazard is based on the third instruction reading a value to be written by the fourth instruction.

### Claim 18

A method comprising:
beginning execution of a first instruction and a second instruction by a processor;
determining that the first instruction and the second instruction both write to a memory location and that a result of the second instruction will be produced for writing to the memory location prior to completion of the first instruction;
based on the determination:
storing the result of the second instruction in a first memory; and
after completion of the first instruction, storing the result of the second instruction at the memory location; and
storing an intermediate result of a third instruction in the first memory.

### Claim 19 (depends on 18)

The method of claim 18, wherein:
the execution of the first instruction is performed by a first functional unit of the processor; and
the execution of the second instruction is performed by a second functional unit of the processor.

### Claim 20 (depends on 18)

The method of claim 18, wherein the storing of the intermediate result of the third instruction is based on a hazard associated with the third instruction.