# US 12,223,318 B2 · Apparatus and method for managing unsupported instruction set architecture (ISA) features in a virtualized environment > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,223,318 B2 - Document ID: US12223318B2 - Status: Granted - Kind: B2 - Application number: 17/214,572 - Filed: 2021-03-26 - Published: 2022-09-29 - Granted: 2025-02-11 - Earliest claimed: 2021-03-26 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Tyler Sondag; David Sheffield; Sofia Pediaditaki - Web page: https://patentgrep.com/patent/US12223318B2 ## CPC - G06F 9/223: {Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems} - G06F 9/3016: {Decoding the operand specifier, e.g. specifier format} - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/3017: {Runtime instruction translation, e.g. macros} - G06F 9/30174: {for non-native instruction set, e.g. Javabyte, legacy code} - G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)} - G06F 9/455: Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines - G06F 9/45558: {Hypervisor-specific management and integration aspects} - G06F 8/41: Compilation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus and method for supporting deprecated instructions. For example, one embodiment of a processor comprises: A processor comprising: a plurality of cores, each core comprising a current microarchitecture to execute instructions and process data, the current microarchitecture including hardware support for virtual execution environment comprising a hypervisor running at a first privilege level and one or more virtual machines each running at a second privilege level, the microarchitecture further including partial hardware support for executing deprecated instructions associated with a prior microarchitecture; at least one core of the plurality of cores comprising: a decoder to decode the instructions, the decoder to specify one or more microoperations corresponding to each of the instructions; execution circuitry to execute the corresponding microoperations; wherein either a first type or a second type of virtual machine exit is to be performed responsive to detecting a deprecated instruction in a first virtual machine, wherein responsive to the first type of virtual machine exit, the hypervisor is to perform a first emulation of the prior microarchitecture without reliance on the partial hardware support, and wherein responsive to the second type of virtual machine exit, the hypervisor is to perform a second emulation of the prior microarchitecture relying on the partial hardware support. ## Claims ### Claim 1 A processor comprising: a plurality of cores, each core comprising a current microarchitecture to execute instructions and process data, the current microarchitecture including hardware support for virtual execution environment comprising a hypervisor running at a first privilege level and one or more virtual machines each running at a second privilege level, the microarchitecture further including partial hardware support for executing deprecated instructions associated with a prior microarchitecture; at least one core of the plurality of cores comprising: a decoder to decode the instructions, the decoder to specify one or more microoperations corresponding to each of the instructions; execution circuitry to execute the corresponding microoperations; wherein either a first type or a second type of virtual machine exit is to be performed responsive to detecting a deprecated instruction in a first virtual machine, wherein responsive to the first type of virtual machine exit, the hypervisor is to perform a first emulation of the prior microarchitecture without reliance on the partial hardware support, and wherein responsive to the second type of virtual machine exit, the hypervisor is to perform a second emulation of the prior microarchitecture relying on the partial hardware support. ### Claim 2 (depends on 1) The processor of claim 1 wherein the partial hardware support comprises microcode including one or more emulation microoperations to execute the deprecated instruction on the execution circuitry. ### Claim 3 (depends on 1) The processor of claim 1 wherein the first type of virtual machine exit comprises or is to be triggered by a first type of exception. ### Claim 4 (depends on 2) The processor of claim 2 wherein the hardware support comprises one or more microarchitectural components including one or more registers for storing state values and/or execution circuits for executing the emulation microoperations. ### Claim 5 (depends on 4) The processor of claim 4 wherein the second type of virtual machine exit is to specify parameters associated with the deprecated instruction, the parameters to be used to execute the emulation microoperations. ### Claim 6 (depends on 5) The processor of claim 5 wherein upon completion of the first emulation or the second emulation, the hypervisor is to provide results and return control to the first virtual machine. ### Claim 7 (depends on 3) The processor of claim 3 wherein the first type of exception comprises an invalid or undefined opcode exception. ### Claim 8 (depends on 7) The processor of claim 7 wherein the second type of virtual machine exit comprises or is to be triggered by a second type of exception, the second type of exception to specify parameters associated with the deprecated instruction. ### Claim 9 A method comprising: executing instructions on at least one core of a plurality of cores, each having a current microarchitecture including hardware support for virtual execution environment comprising a hypervisor running at a first privilege level and one or more virtual machines each running at a second privilege level, the microarchitecture further including partial hardware support for executing deprecated instructions associated with a prior microarchitecture; performing either a first type or a second type of virtual machine exit responsive to detecting a deprecated instruction in a first virtual machine, performing by the hypervisor, responsive to the first type of virtual machine exit, a first emulation of the prior microarchitecture without reliance on the partial hardware support, and performing by the hypervisor, responsive to the first type of virtual machine exit, a second emulation of the prior microarchitecture relying on the partial hardware support. ### Claim 10 (depends on 9) The method of claim 9 wherein the partial hardware support comprises microcode including one or more emulation microoperations to execute the deprecated instruction on the execution circuitry. ### Claim 11 (depends on 9) The method of claim 9 wherein the first type of virtual machine exit comprises or is to be triggered by a first type of exception. ### Claim 12 (depends on 10) The method of claim 10 wherein the hardware support comprises one or more microarchitectural components including one or more registers for storing state values and/or execution circuits for executing the emulation microoperations. ### Claim 13 (depends on 12) The method of claim 12 wherein the second type of virtual machine exit is to specify parameters associated with the deprecated instruction, the parameters to be used to execute the emulation microoperations. ### Claim 14 (depends on 13) The method of claim 13 wherein upon completion of the first emulation or the second emulation, the hypervisor is to provide results and return control to the first virtual machine. ### Claim 15 (depends on 11) The method of claim 11 wherein the first type of exception comprises an invalid or undefined opcode exception. ### Claim 16 (depends on 15) The method of claim 15 wherein the second type of virtual machine exit comprises or is to be triggered by a second type of exception, the second type of exception to specify parameters associated with the deprecated instruction. ### Claim 17 A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of: executing instructions on at least one core of a plurality of cores, each having a current microarchitecture including hardware support for virtual execution environment comprising a hypervisor running at a first privilege level and one or more virtual machines each running at a second privilege level, the microarchitecture further including partial hardware support for executing deprecated instructions associated with a prior microarchitecture; performing either a first type or a second type of virtual machine exit responsive to detecting a deprecated instruction in a first virtual machine, performing by the hypervisor, responsive to the first type of virtual machine exit, a first emulation of the prior microarchitecture without reliance on the partial hardware support, and performing by the hypervisor, responsive to the first type of virtual machine exit, a second emulation of the prior microarchitecture relying on the partial hardware support. ### Claim 18 (depends on 17) The non-transitory machine-readable medium of claim 17 wherein the partial hardware support comprises microcode including one or more emulation microoperations to execute the deprecated instruction on the execution circuitry. ### Claim 19 (depends on 17) The non-transitory machine-readable medium of claim 17 wherein the first type of virtual machine exit comprises or is to be triggered by a first type of exception. ### Claim 20 (depends on 18) The non-transitory machine-readable medium of claim 18 wherein the hardware support comprises one or more microarchitectural components including one or more registers for storing state values and/or execution circuits for executing the emulation microoperations. ### Claim 21 (depends on 20) The non-transitory machine-readable medium of claim 20 wherein the second type of virtual machine exit is to specify parameters associated with the deprecated instruction, the parameters to be used to execute the emulation microoperations. ### Claim 22 (depends on 21) The non-transitory machine-readable medium of claim 21 wherein upon completion of the first emulation or the second emulation, the hypervisor is to provide results and return control to the first virtual machine. ### Claim 23 (depends on 19) The non-transitory machine-readable medium of claim 19 wherein the first type of exception comprises an invalid or undefined opcode exception. ### Claim 24 (depends on 23) The non-transitory machine-readable medium of claim 23 wherein the second type of virtual machine exit comprises or is to be triggered by a second type of exception, the second type of exception to specify parameters associated with the deprecated instruction.