# US 12,223,252 B2 · Through-silicon via in integrated circuit packaging

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- Number: US 12,223,252 B2
- Document ID: US12223252B2
- Status: Granted
- Kind: B2
- Application number: 18/171,072
- Filed: 2023-02-17
- Published: 2023-06-29
- Granted: 2025-02-11
- Earliest claimed: 2018-07-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Fong-yuan Chang; Chin-Chou Liu; Chin-Her Chien; Cheng-Hung Yeh; Po-Hsiang Huang; Sen-Bor Jan; Yi-Kan Cheng; Hsiu-Chuan Shu
- Web page: https://patentgrep.com/patent/US12223252B2

## CPC

- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

## Claims

### Claim 1

A structure, comprising:
a substrate comprising first and second surfaces;
a through-silicon-via (TSV) structure disposed in the substrate, wherein a first end portion of the TSV structure extends over the first surface of the substrate and a second end portion of the TSV structure extends below the second surface of the substrate;
a pseudo metal layer disposed on the first end portion of the TSV structure;
a via disposed on the pseudo metal layer;
a first interconnect structure disposed on the via; and
a second interconnect structure disposed on the second end portion of the TSV structure.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the pseudo metal layer is in contact with the first end portion of the TSV structure.

### Claim 3 (depends on 1)

The structure of claim 1, wherein the pseudo metal layer is non-overlapping with the substrate.

### Claim 4 (depends on 1)

The structure of claim 1, wherein a width of the pseudo metal layer is substantially equal to a width of the TSV structure.

### Claim 5 (depends on 1)

The structure of claim 1, wherein the second interconnect structure is in contact with the second end portion of the TSV structure.

### Claim 6 (depends on 1)

The structure of claim 1, further comprising an other pseudo metal layer disposed on the second end portion of the TSV structure.

### Claim 7 (depends on 1)

The structure of claim 1, wherein a first end of the via is in contact with the pseudo metal layer and a second end of the via is in contact with the first interconnect structure.

### Claim 8 (depends on 1)

The structure of claim 1, further comprising an other via disposed between the second interconnect structure and the second end portion of the TSV structure.

### Claim 9 (depends on 1)

The structure of claim 1, further comprising an other via, wherein a first end of the other via is in contact with the second end portion of the TSV structure and a second end of the other via is in contact with the second interconnect structure.

### Claim 10 (depends on 1)

The structure of claim 1, further comprising:
an other pseudo metal layer disposed on the second end portion of the TSV structure; and
an other via, wherein a first end of the other via is in contact with the other pseudo metal layer and a second end of the other via is in contact with the second interconnect structure.

### Claim 11

A structure, comprising:
a semiconductor substrate;
a through-silicon-via (TSV) disposed in the semiconductor substrate;
a dummy metal layer disposed on and in contact with a first end surface of the TSV and is non-overlapping with the semiconductor substrate;
a first metal line disposed on a second end surface of the TSV;
a via disposed on and in contact with the dummy metal layer; and
a second metal line disposed on the via.

### Claim 12 (depends on 11)

The structure of claim 11, wherein the dummy metal layer is separated from the semiconductor substrate by a portion of the TSV.

### Claim 13 (depends on 11)

The structure of claim 11, wherein the first end surface of the TSV is non-coplanar with a top surface of the semiconductor substrate.

### Claim 14 (depends on 11)

The structure of claim 11, further comprising an other dummy metal layer disposed between the TSV and the first metal line.

### Claim 15 (depends on 11)

The structure of claim 11, further comprising a second via disposed between the second end surface of the TSV and the first metal line.

### Claim 16 (depends on 11)

The structure of claim 11, wherein a width of the first metal line is greater than a width of the TSV; and
wherein the first metal line is in contact with the TSV.

### Claim 17

A structure, comprising:
a substrate;
a through-silicon-via (TSV) disposed in the substrate, wherein a first portion of the TSV extends over a first surface of the substrate and a second portion of the TSV extends below a second surface of the substrate;
a via disposed on the first portion of the TSV;
a first interconnect structure disposed on the via; and
a second interconnect structure disposed on the second portion of the TSV.

### Claim 18 (depends on 17)

The structure of claim 17, further comprising an other via disposed between the TSV and the second interconnect structure.

### Claim 19 (depends on 17)

The structure of claim 17, wherein the second interconnect structure is in contact with the second portion of the TSV.

### Claim 20 (depends on 17)

The structure of claim 17, further comprising a pseudo metal layer disposed between the via and the first portion of the TSV.