# US 12,223,248 B1 · System, method, and computer program product for optimization-based printed circuit board design

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- Number: US 12,223,248 B1
- Document ID: US12223248B1
- Status: Granted
- Kind: B1
- Application number: 16/989,058
- Filed: 2020-08-10
- Granted: 2025-02-11
- Earliest claimed: 2020-08-10
- Assignees: Cadence Design Systems, Inc.
- Applicants: Cadence Design Systems, Inc.
- Inventors: Joydeep Mitra; John Robert Murphy; Zachary Joseph Zumbo; Luke Roberto; Taylor Elsom Hogan
- Web page: https://patentgrep.com/patent/US12223248B1

## CPC

- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/27: using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
- G06F 30/31: Design entry, e.g. editors specifically adapted for circuit design
- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06N 3/006: based on simulated virtual individual or collective life forms, e.g. social simulations or particle swarm optimisation [PSO]
- G06N 3/045: Combinations of networks
- G06N 3/08: Learning methods
- G06N 3/126: Evolutionary algorithms, e.g. genetic algorithms or genetic programming
- G06F 2111/06: Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA]
- G06F 2115/12: Printed circuit boards [PCB] or multi-chip modules [MCM]
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

The present disclosure relates to electronic circuit design, and more specifically, to training a neural network to serve as the reward function for optimization-based approaches to PCB design automation. Embodiments may include generating, using a processor, one or more placed designs using a genetic optimization methodology including a reward function and adjusting the one or more placed designs and the reward function during the generating. Embodiments may further include routing the one or more placed designs using an auto-router to assign a routability score label and training a neural network, using the one or more placed designs and the routability score label, to extract one or more intermediate features from the one or more placed designs. Embodiments may also include predicting a routability of the PCB design based upon, at least in part, the one or more intermediate features.

## Claims

### Claim 1

A computer implemented method associated with a printed circuit board (“PCB”) design, comprising:
generating, using a processor, one or more placed PCB designs using a genetic optimization methodology including a reward function;
adjusting the one or more placed PCB designs and the reward function during the generating;
routing the one or more placed PCB designs using an auto-router to assign a routability score label;
training a neural network architecture, using the one or more placed PCB designs and the routability score label, to extract one or more intermediate features from the one or more placed PCB designs, wherein the neural network architecture includes:
a convolutional neural network (“CNN”) that processes image data representations of the one or more PCB designs,
a graph convolutional network (“GCN”) that processes graph data representations of the one or more PCB designs,
a first deep neural network (“DNN”) that processes scalar data representations of the one or more PCB designs, and
a second DNN that extracts the one or more intermediate features from outputs of the CNN, the GCN, and the first DNN; and
predicting a routability of the PCB design using the second DNN based upon, at least in part, the one or more intermediate features, wherein routability relates to a percentage of successfully routed connections between components of the PCB design.

### Claim 2 (depends on 1)

The computer implemented method of claim 1, wherein the reward function is a wire-crossings based reward function.

### Claim 3 (depends on 1)

The computer implemented method of claim 1, wherein the one or more placed PCB designs includes image data.

### Claim 4 (depends on 1)

The computer implemented method of claim 1, wherein the one or more placed PCB designs includes graph data.

### Claim 5 (depends on 1)

The computer implemented method of claim 1, wherein the one or more placed PCB designs includes scalar data.

### Claim 6

A non-transitory computer readable medium having stored thereon instructions, which when executed by a processor result in one or more operations, the operations comprising:
generating, using a processor, one or more placed PCB designs using a genetic optimization methodology including a reward function;
adjusting the one or more placed PCB designs and the reward function during the generating;
routing the one or more placed PCB designs using an auto-router to assign a routability score label;
training a neural network architecture, using the one or more placed PCB designs and the routability score label, to extract one or more intermediate features from the one or more placed PCB designs, wherein the neural network architecture includes:
a convolutional neural network (“CNN”) that processes image data representations of the one or more PCB designs,
a graph convolutional network (“GCN”) that processes graph data representations of the one or more PCB designs,
a first deep neural network (“DNN”) that processes scalar data representations of the one or more PCB designs, and
a second DNN that extracts the one or more intermediate features from outputs of the CNN, the GCN, and the first DNN; and
predicting a routability of the PCB design using the second DNN based upon, at least in part, the one or more intermediate features, wherein routability relates to a percentage of successfully routed connections of the PCB design.

### Claim 7 (depends on 6)

The computer readable medium of claim 6, wherein the reward function is a wire-crossings based reward function.

### Claim 8 (depends on 6)

The computer readable medium of claim 6, wherein the one or more placed PCB designs includes image data.

### Claim 9 (depends on 6)

The computer readable medium of claim 6, wherein the one or more placed PCB designs includes graph data.

### Claim 10 (depends on 6)

The computer readable medium of claim 6, wherein the one or more placed PCB designs includes scalar data.

### Claim 11

A system associated with a printed circuit board (“PCB”) design, comprising:
a processor configured to generate one or more placed PCB designs using a genetic optimization methodology including a reward function and to adjust the one or more placed PCB designs and the reward function during the generating, the processor further configured to route the one or more placed PCB designs using an auto-router to assign a routability score label, the processor further configured to train a neural network architecture, using the one or more placed PCB designs and the routability score label, to extract one or more intermediate features from the one or more placed PCB designs, wherein the neural network architecture includes: a convolutional neural network (“CNN”) that processes image data representations of the one or more PCB designs, a graph convolutional network (“GCN”) that processes graph data representations of the one or more PCB designs, a first deep neural network (“DNN”) that processes scalar data representations of the one or more PCB designs, and a second DNN that extracts the one or more intermediate features from outputs of the CNN, the GCN, and the first DNN, the processor further configured to predict a routability of the PCB design using the second DNN based upon, at least in part, the one or more intermediate features, wherein routability relates to a percentage of successfully routed connections of the PCB design.

### Claim 12 (depends on 11)

The system of claim 11 wherein the reward function is a wire-crossings based reward function.