# US 12,223,247 B2 · Logic cell structures and related methods > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,223,247 B2 - Document ID: US12223247B2 - Status: Granted - Kind: B2 - Application number: 18/472,280 - Filed: 2023-09-22 - Published: 2024-01-11 - Granted: 2025-02-11 - Earliest claimed: 2021-04-16 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Ltd. - Inventors: Kumar Lalgudi; Ranjith Kumar; Mohammed Rabiul Islam; Jianyang Xu - Web page: https://patentgrep.com/patent/US12223247B2 ## CPC - G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods - G06F 30/373: Design optimisation - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 30/337: Design optimisation - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 2119/06: Power analysis or power optimisation - G06F 2119/12: Timing analysis or timing optimisation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay. ## Claims ### Claim 1 A method of making an integrated circuit structure, the method comprising: addressing a timing condition of a logic cell having a plurality of inputs by allocating a current-driving capability of the logic cell unequally among the plurality of inputs without substantially changing a size of the logic cell. ### Claim 2 (depends on 1) The method of claim 1, wherein the current-driving capability is provided by a plurality of transistor segments of the logic cell, each plurality of transistor segments comprising a control terminal. ### Claim 3 (depends on 2) The method of claim 2, wherein the plurality of transistor segments are FETs and the control terminal is a gate. ### Claim 4 (depends on 2) The method of claim 2, wherein allocating a current-driving capability of the logic cell unequally among the plurality of inputs comprises: connecting a first input of the plurality of inputs to a first number of transistor segments that is larger than other numbers of transistor segments connected to the other inputs. ### Claim 5 (depends on 2) The method of claim 2, wherein allocating a current-driving capability of the logic cell unequally among the plurality of inputs comprises: determining a delay associated with at least one of the plurality of inputs; determining whether the delay is timing-critical; and in response to the determination that the delay is timing-critical, adding an additional transistor segment connected to the input associated with the determined delay. ### Claim 6 (depends on 5) The method of claim 5, wherein each of the plurality of transistor segments has a substantially identical channel width. ### Claim 7 (depends on 2) The method of claim 2, wherein allocating a current-driving capability of the logic cell unequally among the plurality of inputs comprises: determining a delay associated with at least one of the plurality of inputs; determining whether the delay is timing-critical; and in response to the determination that the delay not is timing-critical, removing a transistor segment connected to the input node associated with the determined delay from the plurality of the transistor segments. ### Claim 8 (depends on 2) The method of claim 2, wherein each of the plurality of transistor segments is associated with a substantially identical current-driving capability. ### Claim 9 (depends on 1) The method of claim 1, further comprising: fabricating the logic cell structure on a semiconductor wafer. ### Claim 10 A non-transitory computer-readable storage medium comprising executable instructions that, when executed, causes a processor to perform a method comprising: addressing a timing condition of a logic cell having a plurality of inputs by allocating a current-driving capability of the logic cell unequally among the plurality of inputs without substantially changing a size of the logic cell. ### Claim 11 (depends on 10) The non-transitory computer-readable storage medium of claim 10, wherein the current-driving capability is provided by a plurality of transistor segments of the logic cell, each plurality of transistor segments comprising a control terminal. ### Claim 12 (depends on 11) The non-transitory computer-readable storage medium of claim 11, wherein the plurality of transistor segments are FETs and the control terminal is a gate. ### Claim 13 (depends on 11) The non-transitory computer-readable storage medium of claim 11, wherein allocating a current-driving capability of the logic cell unequally among the plurality of inputs comprises: connecting a first input of the plurality of inputs to a first number of transistor segments that is larger than other numbers of transistor segments connected to the other inputs. ### Claim 14 (depends on 11) The non-transitory computer-readable storage medium of claim 11, wherein allocating a current-driving capability of the logic cell unequally among the plurality of inputs comprises: determining a delay associated with at least one of the plurality of inputs; determining whether the delay is timing-critical; and in response to the determination that the delay is timing-critical, adding an additional transistor segment connected to the input associated with the determined delay. ### Claim 15 (depends on 11) The non-transitory computer-readable storage medium of claim 11, wherein allocating a current-driving capability of the logic cell unequally among the plurality of inputs comprises: determining a delay associated with at least one of the plurality of inputs; determining whether the delay is timing-critical; and in response to the determination that the delay not is timing-critical, removing a transistor segment connected to the input node associated with the determined delay from the plurality of the transistor segments. ### Claim 16 (depends on 11) The non-transitory computer-readable storage medium of claim 11, wherein each of the plurality of transistor segments is associated with a substantially identical current-driving capability. ### Claim 17 (depends on 16) The non-transitory computer-readable storage medium of claim 16, wherein each of the plurality of transistor segments has a substantially identical channel width. ### Claim 18 A method of making an integrated circuit structure, the method comprising: providing a logic cell structure comprising a first input node and a second input node; allocating a first current-driving capability of the first input node; and allocating a second current-driving capability of the second input node; wherein the first and second current-driving capabilities are provided by a plurality of transistor segments of the integrated circuit structure, each plurality of transistor segments comprising a control terminal, and wherein the first current-driving capability is different from the second current-driving capability. ### Claim 19 (depends on 18) The method of claim 18, wherein the plurality of transistor segments are FETs and the control terminal is a gate. ### Claim 20 (depends on 18) The method of claim 18, wherein each of the plurality of transistor segments is associated with a substantially identical current-driving capability.