# US 12,223,246 B2 · Systems, methods, and computer program products for transistor compact modeling using artificial neural networks > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,223,246 B2 - Document ID: US12223246B2 - Status: Granted - Kind: B2 - Application number: 17/465,361 - Filed: 2021-09-02 - Published: 2022-04-14 - Granted: 2025-02-11 - Earliest claimed: 2020-10-13 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jing Wang; Woosung Choi - Web page: https://patentgrep.com/patent/US12223246B2 ## CPC - G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods - G06N 3/084: Backpropagation, e.g. using gradient descent - G06F 30/27: using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model - G06N 3/0499: Feedforward networks - G06N 3/08: Learning methods - G06N 3/082: modifying the architecture, e.g. adding, deleting or silencing nodes or connections - G06N 3/09: Supervised learning - G06F 2119/02: Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA] - G06N 3/048: Activation functions - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A computer implemented method for determining performance of a semiconductor device is provided. The method includes providing training data comprising input state values and training capacitance values to a neural network executing on a computer system; processing the input state values through the neural network to generate modeled charge values; converting the modeled charge values to modeled capacitance values; determining, by the computer system, whether the training capacitance values of the training data are within a threshold value of the modeled capacitance values utilizing a loss function that omits the modeled charge values; and in response to determining that the training capacitance values of the training data are within the threshold value of the modeled capacitance values, converting, by the computer system, the neural network to a circuit simulation code to generate a converted neural network. ## Claims ### Claim 1 A computer implemented method for analyzing performance of a semiconductor device, the method comprising: providing training data comprising input state values and training capacitance values to a neural network executing on a computer system; processing the input state values through the neural network to generate modeled charge values; converting the modeled charge values to modeled capacitance values; determining, by the computer system, whether the training capacitance values of the training data are within a threshold value of the modeled capacitance values utilizing a loss function that omits the modeled charge values; in response to determining that the training capacitance values of the training data are within the threshold value of the modeled capacitance values, converting, by the computer system, the neural network to a circuit simulation code to generate a converted neural network; using the converted neural network to simulate behavior of a test semiconductor device to generate simulation output; determining, by the computer system, whether a turnaround time of the generation of the simulation output is satisfactory; and in response to determining that the turnaround time is not satisfactory, decreasing, by the computer system, the size of the neural network and repeating the processing of the input state values through the neural network. ### Claim 2 (depends on 1) The computer implemented method of claim 1, further comprising, in response to determining that the training capacitance values of the training data are not within the threshold value of the modeled capacitance values, adjusting, by the computer system, a parameter of the neural network and repeating the processing of the input state values through the neural network. ### Claim 3 (depends on 1) The computer implemented method of claim 1, wherein adjusting, by the computer system, a parameter of the neural network includes increasing a size of the neural network. ### Claim 4 (depends on 1) The computer implemented method of claim 1, wherein the semiconductor device is a transistor. ### Claim 5 (depends on 1) The computer implemented method of claim 1, wherein the input state values comprise a plurality of bias values and a plurality of instance values, and wherein the computer implemented method further comprises: for each instance value of the plurality of instance values, generating an additional neural network by holding the instance value constant and providing the plurality of bias values to the additional neural network as the input state values for the additional neural network. ### Claim 6 (depends on 1) The computer implemented method of claim 1, further comprising: manufacturing a first instance of the semiconductor device; measuring characteristics and/or performance of the first instance of the semiconductor device; and generating the training data based on the measured characteristics and/or performance of the first instance of the semiconductor device. ### Claim 7 (depends on 6) The computer implemented method of claim 6, further comprising: building a hardware description language (HDL) model based on the converted neural network; and manufacturing a second instance of the semiconductor device based on the HDL model. ### Claim 8 (depends on 1) The computer implemented method of claim 1, wherein converting the modeled charge values to modeled capacitance values comprises generating a mathematical derivative of the modeled charge values. ### Claim 9 (depends on 1) The computer implemented method of claim 1, wherein the training capacitance values of the training data are generated by a technology computer aided design (TCAD) system simulation. ### Claim 10 (depends on 9) The computer implemented method of claim 9, wherein providing the training data is performed without performing a mathematical integration of the training capacitance values. ### Claim 11 A system for analyzing performance of a semiconductor device, the system comprising: a processor; and a memory that stores computer readable code that, when executed, causes the processor to perform operations comprising: providing training data comprising input state values and training capacitance values to a neural network executing on a computer system; processing the input state values through the neural network to generate modeled charge values; converting the modeled charge values to modeled capacitance values; determining, by the computer system, whether the training capacitance values of the training data are within a threshold value of the modeled capacitance values utilizing a loss function that omits the modeled charge values; in response to determining that the training capacitance values of the training data are within the threshold value of the modeled capacitance values, converting, by the computer system, the neural network to a circuit simulation code to generate a converted neural network; using the converted neural network to simulate behavior of a test semiconductor device to generate simulation output; determining, by the computer system, whether a turnaround time of the generation of the simulation output is satisfactory; and in response to determining that the turnaround time is not satisfactory, decreasing, by the computer system, the size of the neural network and repeating the processing of the input state values through the neural network. ### Claim 12 (depends on 11) The system of claim 11, wherein the operations further comprise, in response to determining that the training capacitance values of the training data are not within the threshold value of the modeled capacitance values, adjusting, by the processor, a parameter of the neural network and repeating the processing of the input state values through the neural network. ### Claim 13 (depends on 11) The system of claim 11, wherein adjusting, by the computer system, a parameter of the neural network includes increasing a size of the neural network. ### Claim 14 (depends on 11) The system of claim 11, wherein the input state values comprise a plurality of bias values and a plurality of instance values, and wherein the operations further comprise: for each instance value of the plurality of instance values, generating an additional neural network by holding the instance value constant and providing the plurality of bias values to the additional neural network as the input state values for the additional neural network. ### Claim 15 (depends on 11) The system of claim 11, wherein the operations further comprise: manufacturing a first instance of the semiconductor device; measuring characteristics and/or performance of the first instance of the semiconductor device; and generating the training data based on the measured characteristics and/or performance of the first instance of the semiconductor device. ### Claim 16 (depends on 15) The system of claim 15, wherein the operations further comprise: building a hardware description language (HDL) model based on the converted neural network; and manufacturing a second instance of the semiconductor device based on the HDL model. ### Claim 17 (depends on 11) The system of claim 11, wherein converting the modeled charge values to modeled capacitance values comprises generating a mathematical derivative of the modeled charge values. ### Claim 18 (depends on 11) The system of claim 11, wherein the training capacitance values of the training data are generated by a technology computer aided design (TCAD) system simulation. ### Claim 19 (depends on 18) The system of claim 18, wherein providing the training data is performed without performing a mathematical integration of the training capacitance values. ### Claim 20 A computer program product, comprising: a non-transitory computer readable storage medium storing computer readable program code that, when executed by a processor of an electronic device, causes the processor to perform operations comprising: providing training data comprising input state values and training capacitance values to a neural network executing on a computer system; processing the input state values through the neural network to generate modeled charge values; converting the modeled charge values to modeled capacitance values; determining, by the computer system, whether the training capacitance values of the training data are within a threshold value of the modeled capacitance values utilizing a loss function that omits the modeled charge values; in response to determining that the training capacitance values of the training data are within the threshold value of the modeled capacitance values, converting, by the computer system, the neural network to a circuit simulation code to generate a converted neural network; using the converted neural network to simulate behavior of a test semiconductor device to generate simulation output; determining, by the computer system, whether a turnaround time of the generation of the simulation output is satisfactory; and in response to determining that the turnaround time is not satisfactory, decreasing, by the computer system, the size of the neural network and repeating the processing of the input state values through the neural network.