# US 12,223,208 B2 · Enhanced write performance utilizing program interleave

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,223,208 B2
- Document ID: US12223208B2
- Status: Granted
- Kind: B2
- Application number: 18/513,742
- Filed: 2023-11-20
- Published: 2024-03-14
- Granted: 2025-02-11
- Earliest claimed: 2022-04-22
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Daniel J. Hubbard; Roy Leonard
- Web page: https://patentgrep.com/patent/US12223208B2

## CPC

- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/061: {Improving I/O performance}
- G06F 3/064: {Management of blocks}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 12/0851: {Cache with interleaved addressing}
- G06F 12/0882: Page mode
- G11C 7/1042: {using interleaving techniques, i.e. read-write of one part of the memory while preparing another part}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/10: Programming or data input circuits
- G11C 16/32: Timing circuits
- G06F 12/0607: {Interleaved addressing}
- G06F 12/0871: Allocation or management of cache space
- G06F 12/0888: using selective caching, e.g. bypass
- G06F 2212/1016: Performance improvement
- G06F 2212/214: Solid state disk
- G06F 2212/222: Non-volatile memory
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices
- G11C 7/1045: {Read-write mode select circuits}
- G11C 2211/5641: Multilevel memory having cells with different number of storage levels
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation to write data to a first multiple level cell (XLC) storage including a first XLC block and a second XLC storage including a second XLC block, and causing a first portion of the data to be written to a first number of pages of the first XLC block and a second portion of the data to be written to a second number of pages of the second XLC block using page level interleave. The first number of pages and the second number of pages are defined by an interleave mix including an interleave ratio between a first XLC write mode and a second XLC write mode.

## Claims

### Claim 1

A system comprising:
a memory; and
a processing device, operatively coupled with memory, to perform operations comprising:
initiating a write operation to write data to a first multiple level cell (XLC) storage comprising a first XLC block and a second XLC storage comprising a second XLC block; and
causing a first portion of the data to be written to a first number of pages of the first XLC block and a second portion of the data to be written to a second number of pages of the second XLC block using page level interleave, wherein the first number of pages and the second number of pages are defined by an interleave mix comprising an interleave ratio between a first XLC write mode and a second XLC write mode.

### Claim 2 (depends on 1)

The system of claim 1, wherein the first portion of the data is written in the first XLC write mode and the second portion of the data is written in the second XLC write mode.

### Claim 3 (depends on 1)

The system of claim 1, wherein the first XLC write mode corresponds to a quad-level cell (QLC) write mode.

### Claim 4 (depends on 3)

The system of claim 3, wherein the second XLC write mode corresponds to at least one of: a multi-level cell (MLC) write mode or a triple-level cell (TLC) write mode.

### Claim 5 (depends on 1)

The system of claim 1, wherein the first XLC write mode corresponds to a penta-level cell (PLC) write mode.

### Claim 6 (depends on 5)

The system of claim 5, wherein the second XLC write mode corresponds to at least one of: multi-level cell (MLC) write mode, a triple-level cell (TLC) write mode, or a quad-level cell (QLC) write mode.

### Claim 7 (depends on 1)

The system of claim 1, wherein the first XLC storage and the second XLC storage each comprise quad-level cell (QLC) cells.

### Claim 8

A method comprising:
initiating, by a processing device, a write operation to write data to a first multiple level cell (XLC) storage comprising a first XLC block and a second XLC storage comprising a second XLC block; and
causing, by the processing device, a first portion of the data to be written to a first number of pages of the first XLC block and a second portion of the data to be written to a second number of pages of the second XLC block using page level interleave, wherein the first number of pages and the second number of pages are defined by an interleave mix comprising an interleave ratio between a first XLC write mode and a second XLC write mode.

### Claim 9 (depends on 8)

The method of claim 8, wherein the first portion of the data is written in the first XLC write mode and the second portion of the data is written in the second XLC write mode.

### Claim 10 (depends on 8)

The method of claim 8, wherein the first XLC write mode corresponds to a quad-level cell (QLC) write mode.

### Claim 11 (depends on 10)

The method of claim 10, wherein the second XLC write mode corresponds to at least one of: a multi-level cell (MLC) write mode or a triple-level cell (TLC) write mode.

### Claim 12 (depends on 8)

The method of claim 8, wherein the first XLC write mode corresponds to a penta-level cell (PLC) write mode.

### Claim 13 (depends on 12)

The method of claim 12, wherein the second XLC write mode corresponds to at least one of: multi-level cell (MLC) write mode, a triple-level cell (TLC) write mode, or a quad-level cell (QLC) write mode.

### Claim 14 (depends on 8)

The method of claim 8, wherein the first XLC storage and the second XLC storage each comprise quad-level cell (QLC) cells.

### Claim 15

A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
initiating a write operation to write data to a first multiple level cell (XLC) storage comprising a first XLC block and a second XLC storage comprising a second XLC block; and
causing a first portion of the data to be written to a first number of pages of the first XLC block and a second portion of the data to be written to a second number of pages of the second XLC block using page level interleave, wherein the first number of pages and the second number of pages are defined by an interleave mix comprising an interleave ratio between a first XLC write mode and a second XLC write mode.

### Claim 16 (depends on 15)

The non-transitory computer-readable storage medium of claim 15, wherein the first XLC write mode corresponds to a quad-level cell (QLC) write mode.

### Claim 17 (depends on 16)

The non-transitory computer-readable storage medium of claim 16, wherein the second XLC write mode corresponds to at least one of: a multi-level cell (MLC) write mode or a triple-level cell (TLC) write mode.

### Claim 18 (depends on 15)

The non-transitory computer-readable storage medium of claim 15, wherein the first XLC write mode corresponds to a penta-level cell (PLC) write mode.

### Claim 19 (depends on 18)

The non-transitory computer-readable storage medium of claim 18, wherein the second XLC write mode corresponds to at least one of: multi-level cell (MLC) write mode, a triple-level cell (TLC) write mode, or a quad-level cell (QLC) write mode.

### Claim 20 (depends on 15)

The non-transitory computer-readable storage medium of claim 15, wherein the first XLC storage and the second XLC storage each comprise quad-level cell (QLC) cells.