# US 12,223,207 B2 · Memory component having internal read-modify-write operation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,223,207 B2 - Document ID: US12223207B2 - Status: Granted - Kind: B2 - Application number: 18/487,955 - Filed: 2023-10-16 - Published: 2024-04-11 - Granted: 2025-02-11 - Earliest claimed: 2013-09-24 - Assignees: Rambus Inc. - Applicants: Rambus Inc. - Inventors: Frederick A. Ware; Thomas Vogelsang - Web page: https://patentgrep.com/patent/US12223207B2 ## CPC - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors} - G06F 3/0638: {Organizing or formatting or addressing of data} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0673: {Single storage device} - G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems} - G11C 7/1009: {Data masking during input/output} - G11C 7/1087: {Data input latches} - G11C 7/109: {Control signal input circuits} - G11C 7/1093: {Input synchronization} - G11C 29/023: {in clock generator or timing circuitry} - G11C 29/028: {with adaption or trimming of parameters} - G11C 2029/0411: {Online error correction} - G11C 2207/107: Serial-parallel conversion of data or prefetch - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address. ## Claims ### Claim 1 A memory device comprising: a first memory die; and a second memory die stacked with the first memory die, wherein each of the first memory die and the second memory die comprise: one or more memory banks; a command interface coupled to the one or more memory banks, the command interface to receive, from a memory controller, a read-modify-write command having an associated read address indicating a location in the one or more memory banks and to access read data from the location in the one or more memory banks indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received; a data interface coupled to the one or more memory banks, the data interface to receive write data associated with the read-modify-write command; and an error correction circuit coupled to the data interface and to the one or more memory banks, the error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the one or more memory banks indicated by the read address. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the adjustable delay period is adjustable in view of at least one of a control signal received at a delay element in the memory device, a value specified in the read-modify-write command, or a value maintained in a control register in the memory device, and wherein increasing the adjustable delay period increases a rate at which successive read-modify-write commands are processed. ### Claim 3 (depends on 1) The memory device of claim 1, wherein each of the first memory die and the second memory die further comprise: a plurality of memory bank pairs; and a dedicated error correction circuit associated with each of the plurality of memory bank pairs, wherein a read-modify-write command directed toward each memory bank pair is processed on the dedicated error correction circuit in parallel, such that error detection and correction for a read-modify-write operation for one bank of a memory bank pair proceeds in a staggered fashion with an other bank of the memory bank pair. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the adjustable delay period comprises two column cycle intervals of a system clock, and wherein the error correction circuit is further to: decode the read data and encode the merged data within a same column cycle interval of the system clock, wherein a period of time that transpires when decoding the read data and encoding the merged data within a same column cycle interval is less than a time that transpires when decoding and encoding separately. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the error correction circuit is further to: decode the read data prior to merging the read data with the received write data, wherein to decode the read data, the error correction circuit to correct single bit errors in the read data using an error syndrome in the read data. ### Claim 6 (depends on 1) The memory device of claim 1, wherein to merge the received write data with the read data to form the merged data, the error correction circuit is to combine the write data and the read data using a data mask received with the write data. ### Claim 7 (depends on 1) The memory device of claim 1, wherein the error correction circuit is further to: encode the merged data prior to writing the merged data to the location in the memory bank, wherein to encode the merged data, the error correction circuit to generate an error syndrome for the merged data. ### Claim 8 A memory device comprising: a first memory die; and a second memory die stacked with the first memory die, wherein each of the first memory die and the second memory die comprise: one or more memory banks; and processing logic coupled to the one or more memory banks, wherein the processing logic is configured to: receive, from a memory controller, a read-modify-write command having an associated read address indicating a location in the one or more memory banks; access read data from the location in the one or more memory banks indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received; receive write data associated with the read-modify-write command; merge the received write data with the read data to form a merged data; and write the merged data to the location in the one or more memory banks indicated by the read address. ### Claim 9 (depends on 8) The memory device of claim 8, wherein the adjustable delay period is adjustable in view of at least one of a control signal received at a delay element in the memory device, a value specified in the read-modify-write command, or a value maintained in a control register in the memory device, and wherein increasing the adjustable delay period increases a rate at which successive read-modify-write commands are processed. ### Claim 10 (depends on 8) The memory device of claim 8, wherein each of the first memory die and the second memory die further comprise: a plurality of memory bank pairs; and a dedicated error correction circuit associated with each of the plurality of memory bank pairs, wherein a read-modify-write command directed toward each memory bank pair is processed on the dedicated error correction circuit in parallel, such that error detection and correction for a read-modify-write operation for one bank of a memory bank pair proceeds in a staggered fashion with an other bank of the memory bank pair. ### Claim 11 (depends on 8) The memory device of claim 8, wherein the adjustable delay period comprises two column cycle intervals of a system clock, and wherein the processing logic is further configured to: decode the read data and encode the merged data within a same column cycle interval of the system clock, wherein a period of time that transpires when decoding the read data and encoding the merged data within a same column cycle interval is less than a time that transpires when decoding and encoding separately. ### Claim 12 (depends on 8) The memory device of claim 8, wherein the processing logic is further configured to: decode the read data prior to merging the read data with the received write data, wherein to decode the read data, the processing logic is to correct single bit errors in the read data using an error syndrome in the read data. ### Claim 13 (depends on 8) The memory device of claim 8, wherein to merge the received write data with the read data to form the merged data, the processing logic is to combine the write data and the read data using a data mask received with the write data. ### Claim 14 (depends on 8) The memory device of claim 8, wherein the processing logic is further configured to: encode the merged data prior to writing the merged data to the location in the memory bank, wherein to encode the merged data, the processing logic is to generate an error syndrome for the merged data. ### Claim 15 A method of operation in a memory device, the memory comprising: receiving, from a memory controller, a read-modify-write command having an associated read address indicating a location in one or more memory banks of a first memory die stacked with a second memory die; accessing read data from the location in the one or more memory banks indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received; receiving write data associated with the read-modify-write command; merging the received write data with the read data to form a merged data; and writing the merged data to the location in the one or more memory banks indicated by the read address. ### Claim 16 (depends on 15) The method of claim 15, wherein the adjustable delay period is adjustable in view of at least one of a control signal received at a delay element in the memory device, a value specified in the read-modify-write command, or a value maintained in a control register in the memory device, and wherein increasing the adjustable delay period increases a rate at which successive read-modify-write commands are processed. ### Claim 17 (depends on 15) The method of claim 15, wherein the adjustable delay period comprises two column cycle intervals of a system clock, and wherein the method further comprises: decoding the read data and encode the merged data within a same column cycle interval of the system clock, wherein a period of time that transpires when decoding the read data and encoding the merged data within a same column cycle interval is less than a time that transpires when decoding and encoding separately. ### Claim 18 (depends on 15) The method of claim 15, further comprising: decoding the read data prior to merging the read data with the received write data, wherein decoding the read data comprises correcting single bit errors in the read data using an error syndrome in the read data. ### Claim 19 (depends on 15) The method of claim 15, wherein merging the received write data with the read data to form the merged data comprises combining the write data and the read data using a data mask received with the write data. ### Claim 20 (depends on 15) The method of claim 15, further comprising encoding the merged data prior to writing the merged data to the location in the memory bank, wherein encoding the merged data comprises generating an error syndrome for the merged data.