# US 12,223,188 B2 · Memory interface for initalizing memory and method thereof

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- Number: US 12,223,188 B2
- Document ID: US12223188B2
- Status: Granted
- Kind: B2
- Application number: 17/748,564
- Filed: 2022-05-19
- Published: 2023-07-06
- Granted: 2025-02-11
- Earliest claimed: 2022-01-06
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Raghu Vamsi Krishna Talanki; Archita Khare; Rahul Tarikere Ravikumar; Jinin So; Jonggeon Lee
- Web page: https://patentgrep.com/patent/US12223188B2

## CPC

- G06F 3/0632: {by initialisation or re-initialisation of storage systems}
- G06F 12/0888: using selective caching, e.g. bypass
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F 11/106: {Correcting systematically all correctable errors, i.e. scrubbing}
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 2212/1024: Latency reduction
- G06F 2212/1028: Power efficiency
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory interface for interfacing with a memory device includes a control circuit configured to determine whether a trigger event has occurred for initializing one or more memory locations in the memory device, and initialize the one or more memory locations in the memory device with pre-defined data upon determining the trigger event has occurred.

## Claims

### Claim 1

A memory interface for interfacing with a memory device, the memory interface comprising:
a control circuit configured to determine whether a trigger event has occurred for initializing one or more memory locations in the memory device, and initialize the one or more memory locations in the memory device with pre-defined data upon determining the trigger event has occurred,
wherein the pre-defined data is run-time data from an application running on a computer system including the memory device,
wherein the pre-defined data is stored in one or more registers associated with the computer system.

### Claim 2 (depends on 1)

The memory interface of claim 1, further comprising a cache connected to the control circuit, and the control circuit performs the initialize without using the cache.

### Claim 3 (depends on 2)

The memory interface of claim 2, further comprising a translation lookaside buffer (TLB) connected to the cache, and the control circuit performs the initialize without using the TLB.

### Claim 4 (depends on 2)

The memory interface of claim 2, further comprising a central processing unit (CPU) connected to the cache via a data bus and connected to the control circuit via a signal line separate from the data bus, and the control circuit determines the trigger event has occurred in response to receiving a trigger signal from the CPU through the signal line.

### Claim 5 (depends on 4)

The memory interface of claim 4, the control circuit performs the initialize without using the data bus.

### Claim 6 (depends on 1)

The memory interface of claim 1, wherein the memory is a dynamic random-access memory (DRAM).

### Claim 7 (depends on 1)

The memory interface of claim 1, wherein the control circuit is located within a scrub engine that is configured detect whether an error has occurred in original data in a given one of the memory locations, correct the original data into corrected data upon detecting the error, and write the corrected data to volatile memory.

### Claim 8 (depends on 7)

The memory interface of claim 7, wherein the scrub engine detects whether the error has occurred upon detection of an idle time or a powering on a computer system including the volatile memory.

### Claim 9 (depends on 1)

The memory interface of claim 1, wherein the trigger event indicates one of i) powering on of a computer system including a volatile memory and ii) identification of a request for initializing the one or more memory locations received from an application in the computer system.

### Claim 10 (depends on 1)

The memory interface of claim 1, wherein the control circuit is configured to initialise the one or more memory locations based on a status associated with each of the one or more memory locations, wherein the status indicates whether the initialization of a corresponding memory location among the one or more memory locations has already been performed.

### Claim 11 (depends on 1)

The memory interface of claim 1, wherein the control circuit is further configured to write first data associated with a first location in the memory device to a second location in the memory device, upon receiving a request for transferring the first data from the first location to the second location from an application in a computer system including the memory device.

### Claim 12

A method for interfacing with a memory device, the method comprising:
determining, by a control circuit of a memory interface, whether a trigger event has occurred for initializing one or more memory locations in the memory device; and
initializing, by the control circuit, the one or more memory locations in the memory device with pre-defined data related upon determining the trigger event has occurred,
wherein the pre-defined data is run-time data from an application running on a computer system including the memory device,
wherein the pre-defined data is stored in one or more registers associated with the computer system.

### Claim 13 (depends on 12)

The method of claim 12, wherein the initializing is performed without using a cache connected to the control circuit.

### Claim 14 (depends on 13)

The method of claim 13, wherein the initializing is performed without using a translation lookaside buffer (TLB) connected to the cache.

### Claim 15 (depends on 13)

The method of claim 13, wherein the determining comprises the control circuit determining the trigger event has occurred in response to receiving a trigger signal through a signal line from a central processing unit (CPU) connected to the cache that is separate from a data bus connecting the CPU to the cache.

### Claim 16 (depends on 15)

The method of claim 15, wherein the initializing is performed without using the data bus.

### Claim 17 (depends on 12)

The method of claim 12, wherein the trigger event indicates identification of a request for initializing the one or more memory locations received from an application in the computer system.

### Claim 18

A memory interface for interfacing with a memory device, the memory interface comprising:
a memory controller connected to the memory device;
a cache connected to the memory controller; and
a central processing unit (CPU) connected to the cache via a data bus and connected to the memory controller via signal line separate from the data bus,
wherein the memory controller initializes one or more memory locations of the memory device in response to receiving a trigger signal from the CPU via the signal line.

### Claim 19 (depends on 18)

The memory interface of claim 18, wherein the memory controller comprises a scrub engine to perform a scrub operation on the memory device, and the scrub engine performs the initializing of the one more memory locations.