# US 12,223,184 B2 · Distributed power up for a memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,223,184 B2 - Document ID: US12223184B2 - Status: Granted - Kind: B2 - Application number: 17/737,539 - Filed: 2022-05-05 - Published: 2023-11-09 - Granted: 2025-02-11 - Earliest claimed: 2022-05-05 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Giuseppe Cariello - Web page: https://patentgrep.com/patent/US12223184B2 ## CPC - G06F 3/0625: {Power saving in storage systems} - G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors} - G06F 3/0632: {by initialisation or re-initialisation of storage systems} - G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 3/0688: {Non-volatile semiconductor memory arrays} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods, systems, and devices for distributed power up for a memory system are described. The method may include a memory system receiving, from a host system, a command to initialize a set of memory devices included in a memory system. Upon receiving the command, the memory system may select a first memory device from the set of memory devices and read, from a second memory device in a controller separate from the set of memory devices, a first operational parameter corresponding to the first memory device. The memory system may then read, from the first memory device, a set of second operational parameters, each second operational parameter of the set of second operational parameters corresponding to a respective memory device of the set of memory devices. ## Claims ### Claim 1 A memory system, comprising: a set of memory devices; and processing circuitry coupled with the set of memory devices and configured to cause the memory system to: receive, from a host system, a command to initialize the set of memory devices included in the memory system; select, based at least in part on the command, a first memory device from the set of memory devices using an output of a random number generator; read, from a second memory device in a controller separate from the set of memory devices, a first operational parameter corresponding to the first memory device; perform a first initialization corresponding to the command on a first subset of the set of memory devices according to the first operational parameter, the first subset of the set of memory devices comprising the first memory device; read, from the first memory device, a set of second operational parameters, each second operational parameter of the set of second operational parameters corresponding to a respective memory device of a second subset of the set of memory devices different than the first subset of the set of memory devices; perform, after performing the first initialization and reading the set of second operational parameters, a second initialization corresponding to the command on the second subset of the set of memory devices according to the set of second operational parameters; and select, based at least in part on a second command to initialize the set of memory devices, a third memory device from the set of memory devices using a second output of the random number generator. ### Claim 2 (depends on 1) The memory system of claim 1, wherein the random number generator comprises one of a true random number generator or a pseudo random number generator. ### Claim 3 (depends on 1) The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: select a fourth memory device from the set of memory devices based at least in part on the command. ### Claim 4 (depends on 3) The memory system of claim 3, wherein the processing circuitry is further configured to cause the memory system to: determine whether a first result associated with reading the first operational parameter is a successful result or a failed result; and determine whether a second result associated with reading, from the second memory device, a third operational parameter corresponding to the fourth memory device is the successful result or the failed result, wherein selecting the first memory device is based at least in part on determining the first result and the second result. ### Claim 5 (depends on 4) The memory system of claim 4, wherein, to determine whether the first result associated with reading the first operational parameter is the successful result or the failed result, the processing circuitry is configured to cause the memory system to determine that the first result associated with reading the first operational parameter is the successful result, and to determine whether the second result associated with reading the third operational parameter is the successful result or the failed result, the processing circuitry is configured to cause the memory system to determine that the second result associated with reading the third operational parameter is the failed result. ### Claim 6 (depends on 4) The memory system of claim 4, wherein the processing circuitry is further configured to cause the memory system to: store the first result and the second result in one or more registers. ### Claim 7 (depends on 4) The memory system of claim 4, wherein the processing circuitry is further configured to cause the memory system to: determine, after reading the set of second operational parameters, that the second result comprises the failed result; read, at the controller and from the second memory device, the third operational parameter based at least in part on determining that the second result comprises a failed result; and store the third operational parameter in a latch corresponding to the fourth memory device. ### Claim 8 (depends on 1) The memory system of claim 1, wherein, to read the set of second operational parameters, the processing circuitry is configured to cause the memory system to: read, at the controller, the set of second operational parameters. ### Claim 9 (depends on 1) The memory system of claim 1, wherein the controller comprises error correcting code circuitry for detecting and correcting errors associated with reading operational parameters. ### Claim 10 (depends on 1) The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: store each second operational parameter of the set of second operational parameters in a respective latch corresponding to the respective memory device of the second subset of the set of memory devices. ### Claim 11 (depends on 1) The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: select the second memory device based at least in part on the command. ### Claim 12 (depends on 1) The memory system of claim 1, wherein the first operational parameter and the set of second operational parameters comprise voltage parameters. ### Claim 13 (depends on 1) The memory system of claim 1, wherein the first operational parameter and the set of second operational parameters comprise trims. ### Claim 14 A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of a memory system, cause the memory system to: receive, from a host system, a command to initialize a set of memory devices included in the memory system; select, based at least in part on the command, a first memory device from the set of memory devices using an output of a random number generator; read, from a second memory device in a controller separate from the set of memory devices, a first operational parameter corresponding to the first memory device; perform a first initialization corresponding to the command on a first subset of the set of memory devices according to the first operational parameter, the first subset of the set of memory devices comprising the first memory device; read, from the first memory device, a set of second operational parameters, each second operational parameter of the set of second operational parameters corresponding to a respective memory device of a second subset of the set of memory devices different than the first subset of the set of memory devices; perform, after performing the first initialization and reading the set of second operational parameters, a second initialization corresponding to the command on the second subset of the set of memory devices according to the set of second operational parameters; and select, based at least in part on a second command to initialize the set of memory devices, a third memory device from the set of memory devices using a second output of the random number generator. ### Claim 15 (depends on 14) The non-transitory computer-readable medium of claim 14, wherein the random number generator comprises one of a true random number generator or a pseudo random number generator. ### Claim 16 (depends on 14) The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the processing circuitry of the processing circuitry further cause the memory system to: select a fourth memory device from the set of memory devices based at least in part on the command. ### Claim 17 (depends on 16) The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the processing circuitry of the memory system, further cause the memory system to: determine whether a first result associated with reading the first operational parameter is a successful result or a failed result; and determine whether a second result associated with reading, from the second memory device, a third operational parameter corresponding to the fourth memory device is the successful result or the failed result, wherein selecting the first memory device is based at least in part on determining the first result and the second result. ### Claim 18 (depends on 17) The non-transitory computer-readable medium of claim 17, wherein the instructions to determine whether the first result associated with reading the first operational parameter is the successful result or the failed result, when executed by the processing circuitry of the memory system, cause the memory system to determine that the first result associated with reading the first operational parameter is the successful result, and the instructions to determine whether the second result associated with reading the third operational parameter is the successful result or the failed result, when executed by the processing circuitry of the memory system, cause the memory system to determine that the second result associated with reading the third operational parameter is the failed result. ### Claim 19 (depends on 17) The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processing circuitry of the memory system, further cause the memory system to: store the first result and the second result in one or more registers. ### Claim 20 (depends on 17) The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processing circuitry of the memory system, further cause the memory system to: determine, after reading the set of second operational parameters, that the second result comprises the failed result; read, at the controller and from the second memory device, the third operational parameter based at least in part on determining that the second result comprises a failed result; and store the third operational parameter in a latch corresponding to the fourth memory device. ### Claim 21 (depends on 14) The non-transitory computer-readable medium of claim 14, wherein the instructions to read the set of second operational parameters, when executed by the processing circuitry of the memory system, cause the memory system to: read, at the controller, the set of second operational parameters. ### Claim 22 (depends on 14) The non-transitory computer-readable medium of claim 14, wherein the controller comprises error correcting code circuitry for detecting and correcting errors associated with reading operational parameters. ### Claim 23 A method, comprising: receiving, from a host system, a command to initialize a set of memory devices included in a memory system; selecting, based at least in part on the command, a first memory device from the set of memory devices using an output of a random number generator; reading, from a second memory device in a controller separate from the set of memory devices, a first operational parameter corresponding to the first memory device; performing a first initialization corresponding to the command on a first subset of the set of memory devices according to the first operational parameter, the first subset of the set of memory devices comprising the first memory device; reading, from the first memory device, a set of second operational parameters, each second operational parameter of the set of second operational parameters corresponding to a respective memory device of a second subset of the set of memory devices different than the first subset of the set of memory devices; performing, after performing the first initialization and reading the set of second operational parameters, a second initialization corresponding to the command on the second subset of the set of memory devices according to the set of second operational parameters; and selecting, based at least in part on a second command to initialize the set of memory devices, a third memory device from the set of memory devices using a second output of the random number generator.