# US 12,223,165 B2 · Multicore, multibank, fully concurrent coherence controller

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- Number: US 12,223,165 B2
- Document ID: US12223165B2
- Status: Granted
- Kind: B2
- Application number: 17/875,440
- Filed: 2022-07-28
- Published: 2022-11-24
- Granted: 2025-02-11
- Earliest claimed: 2018-10-15
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Matthew David Pierson; Kai Chirca; Timothy David Anderson
- Web page: https://patentgrep.com/patent/US12223165B2

## CPC

- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0607: {by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device}
- G06F 3/0632: {by initialisation or re-initialisation of storage systems}
- G06F 3/064: {Management of blocks}
- G06F 3/0658: {Controller construction arrangements}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 9/30101: {Special purpose registers}
- G06F 9/30123: {according to context, e.g. thread buffers}
- G06F 9/3897: {with adaptable data path}
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 9/5016: {the resource being the memory}
- G06F 12/0607: {Interleaved addressing}
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0815: Cache consistency protocols
- G06F 12/0828: {with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions}
- G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means
- G06F 12/084: with a shared cache
- G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
- G06F 12/0857: {by multiple requestors}
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/10: Address translation
- G06F 12/1009: using page tables, e.g. page table structures
- G06F 13/124: {where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine}
- G06F 13/1642: {with request queuing}
- G06F 13/1663: {Access to shared memory}
- G06F 13/1668: {Details of memory controller}
- G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)}
- H03M 13/015: {Simulation or testing of codes, e.g. bit error rate [BER] measurements}
- H03M 13/098: {using single parity bit}
- H03M 13/1575: {Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance}
- H03M 13/276: {Interleaving address generation}
- H03M 13/2785: {Interleaver using in-place interleaving, i.e. writing to and reading from the memory is performed at the same memory location}
- G06F 12/0833: {in combination with broadcast means (e.g. for invalidation or updating)}
- G06F 12/0846: Cache with multiple tag or data arrays being simultaneously accessible
- G06F 12/0851: {Cache with interleaved addressing}
- G06F 12/0862: with prefetch
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G06F 2212/1016: Performance improvement
- G06F 2212/1024: Latency reduction
- G06F 2212/1048: Scalability
- G06F 2212/304: In main memory subsystem
- G06F 2212/452: Instruction code
- G06F 2212/6024: History based prefetching
- G06F 2212/657: Virtual address space management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A system includes a multi-core shared memory controller (MSMC). The MSMC includes a snoop filter bank, a cache tag bank, and a memory bank. The cache tag bank is connected to both the snoop filter bank and the memory bank. The MSMC further includes a first coherent slave interface connected to a data path that is connected to the snoop filter bank. The MSMC further includes a second coherent slave interface connected to the data path that is connected to the snoop filter bank. The MSMC further includes an external memory master interface connected to the cache tag bank and the memory bank. The system further includes a first processor package connected to the first coherent slave interface and a second processor package connected to the second coherent slave interface. The system further includes an external memory device connected to the external memory master interface.

## Claims

### Claim 1

A system comprising:
a cache tag bank;
a snoop filter bank coupled to the cache tag bank;
a memory bank coupled to the cache tag bank; and
a controller coupled to the cache tag bank, the controller configured to:
receive a first read request that includes a first address tag;
apply the first address tag to the snoop filter bank to determine that a unique state is associated with the first address tag;
issue a first snoop request to a peripheral in response to determining that the unique state is associated with the first address tag;
if the first snoop request returns a first value, respond to the first read request with the first value; and
if the first snoop request does not return a value, retrieve a second value from the memory bank or from an external memory and respond to the first read request with the second value.

### Claim 2 (depends on 1)

The system of claim 1, wherein the controller is configured to:
receive a second read request that includes a second address tag;
determine that a third value associated with the second address tag is stored in the memory bank; and
determine a snoop state associated with the second address tag.

### Claim 3 (depends on 2)

The system of claim 2, wherein the controller is configured to, in response to the snoop state indicating an invalid state:
retrieve the third value from the memory bank; and
respond to the second read request with the third value.

### Claim 4 (depends on 2)

The system of claim 2, wherein the controller is configured to, in response to the snoop state indicating a shared state:
retrieve the third value from the memory bank; and
respond to the second read request with the third value.

### Claim 5 (depends on 1)

The system of claim 1, wherein the controller is configured to:
receive a write request that includes a second address tag; and
determine that a third value associated with the second address tag is stored in the memory bank; and
determine a snoop state associated with the second address tag.

### Claim 6 (depends on 5)

The system of claim 5, wherein the controller is configured to, in response to the snoop state indicating the unique state or a shared state:
issue a second snoop request to a processor associated with the second address tag to invalidate the third value stored by the processor; and
write a fourth value associated with the second address tag to the memory bank.

### Claim 7 (depends on 5)

The system of claim 5, wherein:
in response to the snoop state indicating an invalid state, the controller is configured to write a fourth value associated with the second address tag to the memory bank.

### Claim 8 (depends on 1)

The system of claim 1, wherein the controller is configured to:
receive a second read request that includes a second address tag; and
determine that a value associated with the second address tag is not stored in the memory bank; and
determine a snoop state associated with the second address tag.

### Claim 9 (depends on 8)

The system of claim 8, wherein:
in response to the snoop state indicating the unique state or a shared state, the controller is configured to issue a second snoop request to a processor associated with the second address tag;
in response to the second snoop request returning a third value, the controller is configured to respond to the second read request with the third value; and
in response to the second snoop request not returning a value, the controller is configured to:
retrieve a fourth value from the external memory; and
respond to the second read request with the fourth value.

### Claim 10 (depends on 8)

The system of claim 8, wherein the controller is configured to, in response to the snoop state indicating an invalid state:
retrieve a third value from the external memory; and
respond to the second read request with the third value.

### Claim 11 (depends on 1)

The system of claim 1, wherein the controller is configured to:
receive a write request that includes a second address tag; and
determine that a value associated with the second address tag is not stored in the memory bank; and
determine a snoop state associated with the second address tag.

### Claim 12 (depends on 11)

The system of claim 11, wherein the controller is configured to, in response to the snoop state indicating the unique state or a shared state:
issue a second snoop request to a processor associated with the second address tag to invalidate a third first value stored by the processor; and
write a fourth value associated with the second address tag to the external memory.

### Claim 13 (depends on 11)

The system of claim 11, wherein:
in response to the snoop state indicating an invalid state, the controller is configured to write a third value associated with the second address tag to the external memory.

### Claim 14

A method comprising:
receiving, at a controller, a read request that includes a first address tag;
applying, by the controller, the first address tag to a plurality of snoop filter banks coupled to a plurality of cache tag banks to determine that a unique state is associated with the first address tag;
issuing, by the controller, a first snoop request to a peripheral in response to determining that the unique state is associated with the first address tag;
if the first snoop request returns a first value, responding, by the controller, to the read request with the first value; and
if the first snoop request does not return a value, retrieving, by the controller, a second value from a plurality of memory banks coupled to the plurality of cache tag banks or from an external memory and respond to the read request with the second value, wherein:
each of the plurality of cache tag banks, the plurality of snoop filter banks, and the plurality of memory banks is coupled by respective cache way lines; and
the controller is configured to access each line of the respective cache way lines in parallel.

### Claim 15 (depends on 14)

The method of claim 14, wherein:
the plurality of cache tag banks includes a common cache tag bank; and
the plurality of snoop filter banks and the plurality of memory banks share the common cache tag bank.

### Claim 16 (depends on 1)

The system of claim 1, wherein the cache tag bank is configured to be shared by the snoop filter bank and the memory bank.

### Claim 17 (depends on 1)

The system of claim 1, wherein:
the cache tag bank is a common cache tag bank; and
the snoop filter bank and the memory bank share the common cache tag bank.

### Claim 18 (depends on 1)

The system of claim 1, wherein the controller is configured to:
determine that the snoop filter bank stores an identifier of the peripheral, wherein the identifier is associated with the first address tag; and
determine that the snoop filter bank indicates that data associated with the first address tag is stored in a cache of the peripheral.

### Claim 19 (depends on 2)

The system of claim 2, wherein the controller is configured to determine that the third value is stored in the memory bank by at least applying the first address tag to the cache tag bank.

### Claim 20 (depends on 4)

The system of claim 4, wherein the controller is configured to retrieve the third value from the memory bank without issuing a snoop request.