# US 12,223,101 B2 · Hardware-based security authentication

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- Number: US 12,223,101 B2
- Document ID: US12223101B2
- Status: Granted
- Kind: B2
- Application number: 18/376,928
- Filed: 2023-10-05
- Published: 2024-01-25
- Granted: 2025-02-11
- Earliest claimed: 2020-12-15
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Gregory Allen North; Per Torstein Roine; Eric Thierry Jean Peeters
- Web page: https://patentgrep.com/patent/US12223101B2

## CPC

- G06F 21/85: interconnection devices, e.g. bus-connected or in-line devices
- G06F 13/287: {Multiplexed DMA (G06F13/30 takes precedence)}
- G06F 15/7807: {System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A system includes a multiplexer, an input/output (I/O) pin, a logic circuit, and a control register. The multiplexer has multiple inputs, an output, and a selection input. The logic circuit is coupled between the multiplexer and the I/O pin. The logic circuit has a first input. The control register includes first and second bit fields corresponding to the I/O pin. The first bit field is coupled to the selection input of the multiplexer, and the second bit field is coupled to the first input of the logic circuit.

## Claims

### Claim 1

A system comprising:
a first logic circuit including an input and an output;
a second logic circuit including an input and an output;
an input/output (I/O) cell circuit including an input coupled to the output of the first logic circuit, wherein the input of the I/O cell circuit is also coupled to the output of the second logic circuit; and
a control register including a first field coupled to the input of the first logic circuit, a second field coupled to the input of the second logic circuit.

### Claim 2 (depends on 1)

The system of claim 1, wherein the control register further includes a third field coupled to the I/O cell circuit.

### Claim 3 (depends on 1)

The system of claim 1, further comprising an authenticator coupled to the first field of the control register.

### Claim 4 (depends on 3)

The system of claim 3, wherein the authenticator is coupled to the second field of the control register.

### Claim 5 (depends on 3)

The system of claim 3, wherein the authenticator includes compare logic coupled to the control register.

### Claim 6 (depends on 5)

The system of claim 5,
wherein the authenticator is configured to receive an address and convert the address to an identifier, and
wherein the compare logic is configured to compare the identifier to a value stored in the control register.

### Claim 7 (depends on 3)

The system of claim 3, wherein the authenticator is configured to:
receive a first request to map the I/O cell circuit to a device; and
update the control register to associate, with the I/O cell circuit, the device specified in the first request.

### Claim 8 (depends on 7)

The system of claim 7, wherein the authenticator is configured to:
responsive to receiving the first request, determine that the I/O cell circuit is not presently mapped to another device; and
update the control register responsive to determining that the I/O cell circuit is not presently mapped to another device.

### Claim 9 (depends on 7)

The system of claim 7, wherein the authenticator is configured to:
receive a second request for connection of the I/O cell circuit to the device; and
update the control register to specify a state indicated in the second request.

### Claim 10 (depends on 9)

The system of claim 9, wherein the second request includes an address, and wherein the authenticator is configured to:
determine that the address matches an identifier stored in the control register; and
responsive to determining that the address matches the identifier, update the control register to specify the state indicated in the second request.

### Claim 11 (depends on 3)

The system of claim 3, wherein the authenticator is configured to:
determine that the first field is set to a connected state;
allow a high-level secure process to read the I/O cell circuit;
allow a device that is mapped to the I/O cell circuit to read the I/O cell circuit; and
prevent all other devices from reading the I/O cell circuit.

### Claim 12 (depends on 1)

The system of claim 1, further comprising a multiplexer including:
a first input coupled to the output of the first logic circuit;
a second input coupled to the output of the second logic circuit; and
an output coupled to the input of the I/O cell circuit.

### Claim 13 (depends on 1)

The system of claim 1,
wherein the control register further includes a third field, and
wherein the system further comprises a first multiplexer including:
an output coupled to the first logic circuit; and
a select line coupled to the third field of the control register.

### Claim 14 (depends on 13)

The system of claim 13,
wherein the control register further includes a fourth field, and
wherein the system further comprises a second multiplexer including:
an output coupled to the second logic circuit; and
a select line coupled to the fourth field of the control register.

### Claim 15

A system comprising:
a first logic circuit including an input and an output;
a second logic circuit including an input and an output;
an input/output (I/O) cell circuit including an input coupled to the output of the first logic circuit, wherein the input of the I/O cell circuit is also coupled to the output of the second logic circuit;
an authenticator; and
a control register including:
a first field coupled to the input of the first logic circuit and coupled to the authenticator;
a second field coupled to the input of the second logic circuit and coupled to the authenticator; and
a third field coupled to the I/O cell circuit.

### Claim 16 (depends on 15)

The system of claim 15,
wherein the authenticator is configured to receive an address and convert the address to an identifier,
wherein the authenticator includes compare logic coupled to the control register, and
wherein the compare logic is configured to compare the identifier to a value stored in the control register.

### Claim 17 (depends on 15)

The system of claim 15, wherein the authenticator is configured to:
receive a first request to map the I/O cell circuit to a device; and
update the control register to associate, with the I/O cell circuit, the device specified in the first request.

### Claim 18 (depends on 1)

The system of claim 1, further comprising a multiplexer including:
a first input coupled to the output of the first logic circuit;
a second input coupled to the output of the second logic circuit; and
an output coupled to the input of the I/O cell circuit.

### Claim 19 (depends on 1)

The system of claim 1,
wherein the control register further includes a third field, and
wherein the system further comprises a first multiplexer including:
an output coupled to the first logic circuit; and
a select line coupled to the third field of the control register.

### Claim 20 (depends on 19)

The system of claim 19,
wherein the control register further includes a fourth field, and
wherein the system further comprises a second multiplexer including:
an output coupled to the second logic circuit; and
a select line coupled to the fourth field of the control register.