# US 12,223,050 B2 · Apparatus for analyzing non-informative firmware and method using the same

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- Number: US 12,223,050 B2
- Document ID: US12223050B2
- Status: Granted
- Kind: B2
- Application number: 18/049,523
- Filed: 2022-10-25
- Published: 2023-05-11
- Granted: 2025-02-11
- Earliest claimed: 2021-11-09
- Assignees: Electronics and Telecommunications Research Institute
- Applicants: Electronics and Telecommunications Research Institute
- Inventors: Dae-Won Kim; Sang-Su Lee; Yong-Je Choi; Byeong-Cheol Choi; Dong-Wook Kang; Yang-Seo Choi
- Web page: https://patentgrep.com/patent/US12223050B2

## CPC

- G06F 21/572: {Secure firmware programming, e.g. of basic input output system [BIOS]}
- G06F 9/3005: {to perform operations for flow control}
- G06F 9/345: of multiple operands or results {(addressing multiple banks G06F12/06)}
- G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Disclosed herein are an apparatus for analyzing non-informative firmware and a method using the apparatus. The method includes detecting a target instruction for firmware analysis in a memory map in non-informative firmware, generating an analysis list based on memory map information corresponding to the target instruction, and generating a visualized analysis result corresponding to the firmware by grouping the entries of the analysis list by preset reference bytes.

## Claims

### Claim 1

A method for analyzing non-informative firmware, comprising:
detecting a target instruction for firmware analysis in a memory map in non-informative firmware;
generating an analysis list based on memory map information corresponding to the target instruction; and
generating a visualized analysis result corresponding to the firmware by grouping entries of the analysis list by preset reference bytes,
wherein the target instruction is a non-informative instruction in which a string related to a memory map hint is not included, and includes a first instruction for executing a branch and a second instruction in which a specific value in a predefined format is used for a register operation without any description, and
wherein the analysis list is generated by inputting a branch target address of the first instruction and the specific value in the predefined format used in the second instruction according to a sequence order.

### Claim 2 (depends on 1)

The method of claim 1, wherein the specific value in the predefined format is a 8-digit or 4-digit value corresponding to a hexadecimal number.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
detecting an unidentified chip based on the visualized analysis result.

### Claim 4 (depends on 3)

The method of claim 3, wherein the unidentified chip is detected using at least one of a method of comparing a memory map included in the visualized analysis result with a normal memory map, a method of comparing the memory map included in the visualized analysis result with a memory map database accumulated based on training, or a method of tracking an unidentified chip using the memory map included in the visualized analysis result, or a combination thereof.

### Claim 5 (depends on 1)

The method of claim 1, wherein the visualized analysis result is generated by grouping the entries of the analysis list by upper four bytes.

### Claim 6

An apparatus for analyzing non-informative firmware, comprising:
a processor for detecting a target instruction for firmware analysis in a memory map in non-informative firmware, generating an analysis list based on memory map information corresponding to the target instruction, and generating a visualized analysis result corresponding to the firmware by grouping entries of the analysis list by preset reference bytes; and
memory for storing the analysis list and the analysis result,
wherein the target instruction is a non-informative instruction in which a string related to a memory map hint is not included, and includes a first instruction for executing a branch and a second instruction in which a specific value in a predefined format is used for a register operation without any description, and
wherein the analysis list is generated by inputting a branch target address of the first instruction and the specific value in the predefined format used in the second instruction according to a sequence order.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the specific value in the predefined format is a 8-digit or 4-digit value corresponding to a hexadecimal number.

### Claim 8 (depends on 6)

The apparatus of claim 6, wherein the processor detects an unidentified chip based on the visualized analysis result.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the processor detects the unidentified chip using at least one of a method of comparing a memory map included in the visualized analysis result with a normal memory map, a method of comparing the memory map included in the visualized analysis result with a memory map database accumulated based on training, or a method of tracking an unidentified chip using the memory map included in the visualized analysis result, or a combination thereof.

### Claim 10 (depends on 6)

The apparatus of claim 6, wherein the visualized analysis result is generated by grouping the entries of the analysis list by upper four bytes.