# US 12,223,011 B1 · Integer matrix multiplication engine using pipelining > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,223,011 B1 - Document ID: US12223011B1 - Status: Granted - Kind: B1 - Application number: 18/519,531 - Filed: 2023-11-27 - Granted: 2025-02-11 - Earliest claimed: 2019-04-01 - Assignees: MIPS Holding, Inc. - Applicants: MIPS Holding, Inc. - Inventors: David John Simpson - Web page: https://patentgrep.com/patent/US12223011B1 ## CPC - G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} - G06F 7/16: Combined merging and sorting - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Techniques for data manipulation using integer matrix multiplication using pipelining are disclosed. A first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n are obtained for matrix multiplication within a processor. The first and second integer matrices employ a two's complement variable radix point data representation. The first and second integer matrices are distilled into (j×j) submatrices. A first variable radix point format and an initial value for an accumulator register are configured dynamically. A first variable radix point format is configured dynamically for the first integer matrix and a second variable radix point format is configured dynamically for the second integer matrix. Multiply-accumulate operations are executed in a pipelined fashion on the (j×j) submatrices of the first integer matrix and the second integer matrix, where a third variable radix point format is configured for the result. ## Claims ### Claim 1 A processor-implemented method comprising: obtaining a first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n for matrix multiplication within a processor, wherein the first integer matrix and the second integer matrix employ a two's complement variable radix point data representation; distilling the first integer matrix and the second integer matrix into (j×j) submatrices; configuring dynamically a first variable radix point format for the first integer matrix and a second variable radix point format for the second integer matrix; and executing matrix-multiplication operations in a pipelined architecture on the (j×j) submatrices of the first integer matrix and the second integer matrix, wherein a third variable radix point format is configured for the result. ### Claim 2 (depends on 1) The method of claim 1 further comprising configuring dynamically at least one of a variable radix point format and an initial value for an accumulator register. ### Claim 3 (depends on 1) The method of claim 1 wherein the first variable radix point format and the second variable radix point format comprise a 16-bit data type. ### Claim 4 (depends on 1) The method of claim 1 wherein the first variable radix point format and the second variable radix point format comprise a 4-bit primitive data type. ### Claim 5 (depends on 1) The method of claim 1 wherein the first variable radix point format and the second variable radix point format comprise an 8-bit primitive data type. ### Claim 6 (depends on 1) The method of claim 1 further comprising outputting results of the matrix multiplication to a storage element. ### Claim 7 (depends on 1) The method of claim 1 wherein the first integer matrix and the second integer matrix comprise subsections of an o-dimensional tensor, wherein o is greater than 2. ### Claim 8 (depends on 1) The method of claim 1 wherein each of one or more multiply-accumulate (MAC) units used for matrix multiplication in the processor is configured to have an accumulator depth of m. ### Claim 9 (depends on 1) The method of claim 1 further comprising pipelining input elements to multiply-accumulate (MAC) units used for matrix multiplication in the processor through two input registers. ### Claim 10 (depends on 1) The method of claim 1 wherein performing N multiply-accumulate (MAC) operations in parallel reduces an amount of time taken to perform the N MAC operations from an order of magnitude of N3 to an order of magnitude of N2. ### Claim 11 (depends on 1) The method of claim 1 further comprising adding one or more idle or no operation (NOP) cycles after completion of a matrix multiply operation before starting a next matrix multiply operation. ### Claim 12 (depends on 1) The method of claim 1 wherein a processor and memory subsystem is allocated as part of one or more clusters within a reconfigurable fabric to implement MAC units. ### Claim 13 (depends on 12) The method of claim 12, wherein each cluster of the one or more clusters within the reconfigurable fabric is controlled by one or more circular buffers. ### Claim 14 (depends on 13) The method of claim 13, wherein the one or more circular buffers are statically scheduled. ### Claim 15 (depends on 12) The method of claim 12, wherein each cluster of the one or more clusters within the reconfigurable fabric comprises process elements, switching elements, or storage elements. ### Claim 16 (depends on 1) The method of claim 1 wherein input elements of the first matrix are taken from a row of the first matrix. ### Claim 17 (depends on 1) The method of claim 1 wherein input elements of the second matrix are taken from a column of the second matrix. ### Claim 18 One or more non-transitory computer readable media embodying one or more instructions that are operable when executed by one or more processors to perform operations of: obtaining a first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n for matrix multiplication within a processor, wherein the first integer matrix and the second integer matrix employ a two's complement variable radix point data representation; distilling the first integer matrix and the second integer matrix into (j×j) submatrices; configuring dynamically a first variable radix point format for the first integer matrix and a second variable radix point format for the second integer matrix; and executing matrix-multiplication operations in a pipelined architecture on the (j×j) submatrices of the first integer matrix and the second integer matrix, wherein a third variable radix point format is configured for the result. ### Claim 19 A system comprising: a memory which stores instructions; and one or more processors coupled to the memory wherein the one or more processors, when executing the instructions, are configured to: obtain a first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n for matrix multiplication within a processor, wherein the first integer matrix and the second integer matrix employ a two's complement variable radix point data representation; distill the first integer matrix and the second integer matrix into (j×j) submatrices; configure dynamically a first variable radix point format for the first integer matrix and a second variable radix point format for the second integer matrix; and execute matrix-multiplication operations in a pipelined architecture on the (j×j) submatrices of the first integer matrix and the second integer matrix, wherein a third variable radix point format is configured for the result.