# US 12,222,890 B2 · Programmable logic device configuration over communication fabrics > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,222,890 B2 - Document ID: US12222890B2 - Status: Granted - Kind: B2 - Application number: 17/846,305 - Filed: 2022-06-22 - Published: 2022-10-06 - Granted: 2025-02-11 - Earliest claimed: 2019-02-01 - Assignees: Liqid Inc. - Applicants: Liqid Inc. - Inventors: James Scott Cannata; Christopher R. Long; Phillip Clark; Sumit Puri - Web page: https://patentgrep.com/patent/US12222890B2 ## CPC - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 9/4411: {Configuring for operating with peripheral devices; Loading of device drivers} - G06F 2213/0026: PCI express - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method of programming a fabric-coupled FPGA device includes instructing a communication fabric to establish a first logical partition segregating a first set of communication switch ports within the communication fabric that includes the management processor and a target device comprising a memory device configured to program a field-programmable gate array (FPGA). The method includes directing configuration data configured to program the FPGA to the target device over the first logical partition. The method includes instructing the communication fabric to remove the first logical partition in the communication fabric, wherein the configuration data remains stored at the target device after removal of the first logical partition. The method includes instructing the communication fabric to establish a second logical partition segregating a second set of communication switch ports within the communication fabric that includes a selected device and the target device that stores the configuration data. ## Claims ### Claim 1 A computing apparatus comprising: one or more computer readable storage media; program instructions stored on the one or more computer readable storage media, that based at least in part on execution by a management processor, direct the management processor to at least: instruct a communication fabric to establish a first logical partition segregating a first set of communication switch ports within the communication fabric that includes the management processor and a target device comprising a memory device configured to program a field-programmable gate array (FPGA); direct configuration data configured to program the FPGA to the target device over the first logical partition; after transfer of the configuration data, instruct the communication fabric to remove the first logical partition in the communication fabric, wherein the configuration data remains stored at the target device after removal of the first logical partition; and instruct the communication fabric to establish a second logical partition segregating a second set of communication switch ports within the communication fabric that includes at least a selected device and the target device that stores the configuration data. ### Claim 2 (depends on 1) The computing apparatus of claim 1, wherein the selected device comprises a central processing unit (CPU), a data storage device, or a network interface element. ### Claim 3 (depends on 1) The computing apparatus of claim 1, wherein the configuration data comprises a programming bitstream to program the FPGA into a programmed state, and wherein the programmed state comprises a target programmed state of programmable logic elements of the FPGA. ### Claim 4 (depends on 1) The computing apparatus of claim 1, wherein the target device further comprises the FPGA. ### Claim 5 (depends on 1) The computing apparatus of claim 1, wherein the management processor comprises a first Peripheral Component Interconnect Express (PCIe) root complex; and wherein the selected device comprises a second PCIe root complex different that the first PCIe root complex. ### Claim 6 (depends on 1) The computing apparatus of claim 1, wherein after the configuration data remains stored at the target device, the configuration data programs the FPGA into a programmed state responsive to a power cycling of at least the FPGA. ### Claim 7 (depends on 1) The computing apparatus of claim 1, comprising further program instructions stored on the one or more computer readable storage media, that based at least in part on execution by the management processor, direct the management processor to at least: receive a user command to establish a compute unit comprising the selected device and the FPGA, wherein the user command indicates the configuration data is to be deployed for the FPGA; and establish the compute unit comprising at least the selected device and the target device. ### Claim 8 (depends on 1) The computing apparatus of claim 1, wherein removal of the first logical partition in the communication fabric comprises de-establishing the first logical partition and placing the target device back into a pool of free devices while the configuration data remains stored at the target device while in the pool. ### Claim 9 A method comprising: instructing, by a management processor, a communication fabric to establish a first logical partition segregating a first set of communication switch ports within the communication fabric that includes the management processor and a target device comprising a memory device configured to program a field-programmable gate array (FPGA); directing configuration data configured to program the FPGA to the target device over the first logical partition; after transfer of the configuration data, instructing, by the management processor, the communication fabric to remove the first logical partition in the communication fabric, wherein the configuration data remains stored at the target device after removal of the first logical partition; and instructing, by the management processor, the communication fabric to establish a second logical partition segregating a second set of communication switch ports within the communication fabric that includes at least a selected device and the target device configured according to the configuration data. ### Claim 10 (depends on 9) The method of claim 9, wherein the selected device comprises one among a central processing unit (CPU), a data storage device, and a network interface element. ### Claim 11 (depends on 9) The method of claim 9, wherein the configuration data comprises a programming bitstream to program the FPGA into a programmed state, and wherein the programmed state comprises a target programmed state of programmable logic elements of the FPGA. ### Claim 12 (depends on 9) The method of claim 9, wherein the target device further comprises the FPGA. ### Claim 13 (depends on 9) The method of claim 9, wherein the management processor comprises a first Peripheral Component Interconnect Express (PCIe) root complex; and wherein the selected device comprises a second PCIe root complex different that the first PCIe root complex. ### Claim 14 (depends on 9) The method of claim 9, wherein after the configuration data remains stored at the target device, the configuration data programs the FPGA into a programmed state responsive to a power cycling of at least the FPGA. ### Claim 15 (depends on 9) The method of claim 9, comprising: receiving a user command to establish a compute unit comprising the selected device and the FPGA, wherein the user command indicates the configuration data is to be deployed for the FPGA; and establish the compute unit comprising at least the selected device and the target device. ### Claim 16 (depends on 9) The method of claim 9, wherein removal of the first logical partition in the PCIe fabric comprises de-establishing the first logical partition and placing the target device back into a pool of free devices while the configuration data remains stored at the target device while in the pool. ### Claim 17 A computing apparatus comprising: a management processor configured to: receive user commands to establish a compute unit among a plurality of physical computing components coupled by a communication fabric, wherein the user command identifies configuration data stored in a storage device accessible to the management processor; and establish the compute unit by: instructing the communication fabric to establish a first partition segregating a first set of communication switch ports within the communication fabric to include the management processor and a target device comprising a memory device configured to program a field-programmable gate array (FPGA); directing at least the configuration data to the target device using the first partition; after transfer of the configuration data over the first partition, instructing the communication fabric to de-establish the first partition including the management controller and the target device, wherein the configuration data remains stored at the target device after de-establishment of the first partition; and instructing the communication fabric to establish a second partition segregating a second set of communication switch ports within the communication fabric including a selected device and the target device, the second partition within the communication fabric configured such that the selected device has visibility over the communication fabric to the target device that stores the configuration data. ### Claim 18 (depends on 17) The computing apparatus of claim 17, wherein the selected device comprises a central processing unit (CPU), and wherein the configuration data comprises a programming bitstream to program the FPGA into the programming state comprising a target programmed state of programmable logic elements of the FPGA. ### Claim 19 (depends on 17) The computing apparatus of claim 17, wherein the target device further comprises the FPGA. ### Claim 20 (depends on 17) The computing apparatus of claim 17, wherein after the configuration data remains stored at the target device, the configuration data programs the FPGA into the programmed state responsive to a power cycling of at least the FPGA.