# US 12,222,884 B2 · Systems and methods for mapping hardware FIFO to processor address space

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- Number: US 12,222,884 B2
- Document ID: US12222884B2
- Status: Granted
- Kind: B2
- Application number: 17/813,123
- Filed: 2022-07-18
- Published: 2022-11-03
- Granted: 2025-02-11
- Earliest claimed: 2017-11-06
- Assignees: The United States of America as represented by the Secretary of the Air Force
- Applicants: Government of the United States as represented by the Secretary of the Air Force
- Inventors: Mark H. Linderman; Qing Wu; Dennis Fitzgerald
- Web page: https://patentgrep.com/patent/US12222884B2

## CPC

- G06F 13/404: {with address mapping}
- F16C 33/741: {by means of a fluid}
- F16J 15/32: with elastic sealings, e.g. O-rings
- G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)}
- G06F 13/4031: {with arbitration}
- G06F 13/4081: {Live connection to bus, e.g. hot-plugging (current or voltage limitation during live insertion H02H9/004)}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- F16C: SHAFTS; FLEXIBLE SHAFTS; ELEMENTS OR CRANKSHAFT MECHANISMS; ROTARY BODIES OTHER THAN GEARING ELEMENTS; BEARINGS
- F16J: PISTONS {(specially adapted for dampers F16F9/32)}; CYLINDERS; SEALINGS
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs.

## Claims

### Claim 1

A method of configuring a microprocessor computer system, wherein said microprocessor computer system comprises:
a plurality of external data streams, each associated with a distinct memory-mapped FIFO; and
a processor core that processes multiple sequential iterations of a vector operation, each iteration requiring the processing of a datum from each of the data streams before proceeding to the next iteration;
said method comprising, for each iteration of the vector operation, configuring said vector operation to access each memory-mapped FIFO in turn and to stall if any such access is invalid.

### Claim 2 (depends on 1)

The method of claim 1, wherein the plurality of external data streams is a plurality of external input data streams;
wherein each of said input data streams in enqueued in a distinct memory-mapped FIFO and said processor core must dequeue and process one datum from each memory-mapped FIFO for each iteration;
wherein an invalid access of a memory-mapped FIFO comprises executing a read operation against an empty FIFO; and
wherein iterating said vector operation results in processing the external input data streams.

### Claim 3 (depends on 1)

The method of claim 1, wherein the plurality of external data streams is a plurality of external output data streams;
wherein each of said output data streams is dequeued from a distinct memory-mapped FIFO and said processor core must enqueue one datum to each memory-mapped FIFO for each iteration;
wherein an invalid access of a memory-mapped FIFO comprises executing a write operation against an full FIFO; and
wherein iterating said vector operation results in generating the external output data streams.

### Claim 4 (depends on 1)

The method of claim 1, wherein said external data streams are synchronously sampled data from a multiplicity of analog-to-digital converters.

### Claim 5 (depends on 1)

The method of claim 1, wherein each said memory-mapped FIFO is accessed by said processor core as an address.

### Claim 6 (depends on 5)

The method of claim 5, wherein the said processor core reads said memory-mapped FIFO by reading said address.

### Claim 7 (depends on 6)

The method of claim 6, wherein said step of reading said address dequeues a value at the head of a queue.

### Claim 8 (depends on 5)

The method of claim 5, wherein said processor core writes to said memory-mapped FIFO by writing said address.

### Claim 9 (depends on 8)

The method of claim 8, wherein said step of writing said address enqueues a value at the head of a queue.

### Claim 10 (depends on 9)

The method of claim 9, wherein said processor core will stall when writing to a full memory-mapped FIFO.

### Claim 11 (depends on 1)

The method of claim 1, wherein when said plurality of external data streams are stored sequentially in said memory-mapped FIFO, said memory-mapped FIFO is addressed by specifying a vector stride of zero.

### Claim 12 (depends on 11)

The method of claim 11, wherein said step of specifying a vector stride of zero reads a same address repeatedly to access all data in said memory-mapped FIFO.

### Claim 13 (depends on 1)

The method of claim 1, wherein when said plurality of external data streams are to be stored sequentially in said memory-mapped FIFO, a write to said memory-mapped FIFO will fill said memory-mapped FIFO when a vector stride of zero is specified.

### Claim 14 (depends on 1)

The method of claim 1, wherein said processor core will read and dequeue data at the head of a non-empty said memory-mapped FIFO and will block said read operation when said memory-mapped FIFO is empty.

### Claim 15 (depends on 1)

The method of claim 1, wherein said processor core will read data at the head of a non-empty said memory-mapped FIFO and will block said read operation when said memory-mapped FIFO is empty.

### Claim 16 (depends on 1)

The method of claim 1, wherein said processor core will read data at the head of a non-empty said memory-mapped FIFO and return an invalid value when said memory-mapped FIFO is empty.

### Claim 17 (depends on 1)

The method of claim 1, wherein said processor core will read and dequeue data at the head of a non-empty said memory-mapped FIFO and will return an invalid value when said memory-mapped FIFO is empty.

### Claim 18 (depends on 17)

The method of claim 17, wherein said processor core remains un-stalled when said invalid value is returned.

### Claim 19 (depends on 16)

The method of claim 16, wherein said processor core remains un-stalled when said invalid value is returned.