# US 12,222,880 B2 · Stacked semiconductor device assembly in computer system

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- Number: US 12,222,880 B2
- Document ID: US12222880B2
- Status: Granted
- Kind: B2
- Application number: 18/216,543
- Filed: 2023-06-29
- Published: 2024-03-28
- Granted: 2025-02-11
- Earliest claimed: 2009-05-26
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Scott C. Best
- Web page: https://patentgrep.com/patent/US12222880B2

## CPC

- G06F 13/362: with centralised access control
- G06F 13/4068: {Electrical coupling}
- G11C 11/408: Address circuits
- G11C 11/409: Read-write [R-W] circuits
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 14/0018: {whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor}
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- H10D 89/60: Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60)
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/90: Bond pads, in general
- H10W 90/00: Package configurations
- H10W 72/01: {Manufacture or treatment}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 90/20: Configurations of stacked chips
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

## Claims

### Claim 1

A memory device, comprising:
a plurality of integrated circuit (IC) chips comprising:
a plurality of memory cores distributed across the plurality of IC chips, each memory core further including a plurality of memory cells; and
a controller coupled to the plurality of memory cores, the controller configured to access the plurality of memory cells of the plurality of memory cores, wherein the controller is distributed across the plurality of IC chips, and comprises at least a channel master circuit of a first IC chip and a channel slave circuit of each of a remainder of the plurality of IC chips;
wherein the plurality of IC chips are stacked one on top of the other, and the remainder of the plurality of IC chips includes at least two IC chips that are aligned with each other, and wherein the first IC chip is configured to be placed directly on a substrate and physically offset from each of the remainder of the plurality of IC chips in a plane that is substantially parallel to the substrate.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the plurality of IC chips are identical to one another.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein each of the plurality of IC chips includes a respective channel master circuit and a respective channel slave circuit, and the respective channel master circuit is coupled to electrostatic discharge protection (ESD) circuitry.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein each of the plurality of IC chips further comprises:
selection circuitry configured to select one of the respective channel master circuit and the respective channel slave circuit to control whether the respective IC chip communicates data with local ESD protection.

### Claim 5 (depends on 3)

The memory device of claim 3, wherein only the ESD circuitry of the first IC chip is enabled, and the ESD circuitry of each of the remainder of the plurality of IC chips is disabled.

### Claim 6 (depends on 3)

The memory device of claim 3, wherein each of the plurality of IC chips further comprises:
selection circuitry coupled to the respective channel master circuit and the respective channel slave circuit of the IC chip, where the selection circuitry is configured to select one of the respective channel master circuit and the respective channel slave circuit of the IC chip.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the selection circuitry of the first IC chip selects the channel master circuit of the first IC chip.

### Claim 8 (depends on 6)

The memory device of claim 6, wherein for each of the plurality of IC chips, the selection circuitry is configured to receive an input, and to determine that the respective IC chip is to communicate data using the channel master circuit or the channel slave circuit based on a voltage level of the input.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein one of the plurality of IC chips is configured to receive the input from an external source or a neighboring IC chip of the plurality of IC chips that is disposed immediately adjacent to the one of the plurality of IC chips.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein:
the channel master circuit of the first IC chip is coupled to two master connection pads that are disposed on opposite sides of a substrate of the first IC chip and aligned with one another.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein the two master connection pads of the first IC chip are electrically coupled to each other by a first through chip via.

### Claim 12 (depends on 1)

The memory device of claim 1, wherein:
the channel slave circuit of each of the remainder of the plurality of IC chips is coupled to two slave connection pads that are disposed on opposite sides of a substrate of a respective remainder IC chip and aligned with one another.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein a master connection pad of the first IC chip is aligned with, and electrically coupled to, the two slave connection pads of each of the remainder of the plurality of IC chips in the memory device, allowing the channel master circuit of the first IC chip to electrically couple to the channel slave circuit of each of the remainder of the plurality of IC chips.

### Claim 14 (depends on 12)

The memory device of claim 12, wherein the two slave connection pads of each of the remainder of the plurality of IC chips are electrically coupled to each other by a second through chip via.

### Claim 15 (depends on 1)

The memory device of claim 1, wherein each memory core includes one of a DRAM memory core, a flash memory core and a processor array core.

### Claim 16 (depends on 1)

The memory device of claim 1, wherein the first IC chip is offset from each of the remainder of the plurality of IC chips along two perpendicular axes that are substantially parallel with two distinct planar sides of the plurality of IC chips.

### Claim 17 (depends on 1)

The memory device of claim 1, wherein the first IC chip is configured to communicate read/write data via the channel master circuit of a first IC chip, and each of the remainder of the plurality of IC chips is configured to communicate read/write data via the channel slave circuit.

### Claim 18 (depends on 1)

The memory device of claim 1, wherein each of the remainder of the plurality of IC chips includes a respective selection pad, wherein each of the remainder of the plurality of IC chips is configured to, when the respective selection pad is left unconnected, communicate data using the channel slave circuit of the respective IC chip of the remainder the plurality of IC chips.