# US 12,222,873 B2 · Method and apparatus to enable a cache (DEVPIC) to store process specific information inside devices that support address translation service (ATS) > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,222,873 B2 - Document ID: US12222873B2 - Status: Granted - Kind: B2 - Application number: 17/473,468 - Filed: 2021-09-13 - Published: 2021-12-30 - Granted: 2025-02-11 - Earliest claimed: 2021-04-29 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Rupin Vakharwala; Vedvyas Shanbhogue - Web page: https://patentgrep.com/patent/US12222873B2 ## CPC - G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] - G06F 12/1036: for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) - G06F 12/1081: for peripheral access to main memory, e.g. direct memory access [DMA] - G06F 13/1668: {Details of memory controller} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 13/4295: {using an embedded synchronisation} - G06F 2212/1004: Compatibility, e.g. with legacy hardware - G06F 2212/1024: Latency reduction - G06F 2212/651: Multi-level translation tables - G06F 2212/657: Virtual address space management - G06F 2212/681: Multi-level TLB, e.g. microTLB and main TLB - G06F 2212/682: Multiprocessor TLB consistency - G06F 2213/0026: PCI express - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to PCIe Address Translation Service (ATS) to allow devices to have a DevTLB that caches address translation (per page) information in conjunction with a Device ProcessInfoCache (DevPIC) that will store process specific information. Other embodiments may be described and/or claimed. ## Claims ### Claim 1 An apparatus comprising: a cache memory having a plurality of entries, each of the plurality of entries to store process specific information for a process; a device translation lookaside buffer (DevTLB) having a plurality of entries each to store a virtual address-to-physical address translation received from an input/output memory management unit (IOMMU); and at least one processor coupled to the cache memory and the DevTLB, wherein the apparatus comprises a Peripheral Component Interconnect Express (PCIe) device to couple with at least one central processing unit (CPU) and a shared virtual memory (SVM), to communicate, to the CPU, capability information to indicate that the PCIe device includes the cache memory to store the process specific information, and enable the cache memory in response to a configuration message from the CPU. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the process specific information includes mask information to indicate one or more address bits of a virtual address to be masked from the IOMMU. ### Claim 3 (depends on 2) The apparatus of claim 2, further comprising a mask circuit to receive a virtual address from the at least one processor and to mask one or more address bits of the virtual address according to the process specific information from an entry of the cache memory, wherein the masked one or more address bits of the virtual address comprises metadata associated with a process. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the apparatus is to receive a physical address from the IOMMU in response to the masked virtual address, the apparatus to send the physical address to the SVM, the PCIe device to couple to the SVM via a root complex, the root complex comprising the IOMMU. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein each of the plurality of entries of the cache memory comprises: a first field to store a process address space identifier; a second field to store a portion of an address space; and a third field to store the process specific information. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the second field is to store the portion of the address space to identify whether the entry is associated with a kernel space of the process or a user space of the process. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the process specific information comprises a domain identifier. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein in response to an invalidation message for a first process having a first domain identifier, the DevTLB is to invalidate entries of the DevTLB associated with the first domain identifier. ### Claim 9 (depends on 1) The apparatus of claim 1, further comprising a configuration storage to store configuration information, the configuration information comprising an indicator to indicate presence of the cache memory, the cache memory comprising a process information cache. ### Claim 10 A method comprising: communicating, from a Peripheral Component Interconnect Express (PCIe) device to a processor, capability information of the PCIe device, the capability information to indicate that the PCIe device includes a process information cache to store process specific information; receiving a configuration message from the processor and enabling the process information cache, in response to the configuration message; receiving first process specific information from an input/output memory management unit (IOMMU); and storing the first process specific information in a first entry of the process information cache in association with a process address space identifier (PASID). ### Claim 11 (depends on 10) The method of claim 10, further comprising storing the first process specific information in the first entry of the process information cache in association with one of a kernel address space or a user address space. ### Claim 12 (depends on 10) The method of claim 10, further comprising receiving the first process specific information in response to a request from the process information cache to the IOMMU. ### Claim 13 (depends on 12) The method of claim 12, further comprising sending the request to the IOMMU in response to a read request to a first virtual address from a processing circuit of the PCIe device. ### Claim 14 (depends on 13) The method of claim 13, further comprising: using a mask included in the process specific information to mask at least a portion of the first virtual address; and sending the masked first virtual address to a device translation lookaside buffer to obtain a physical address corresponding to the first virtual address, to enable the processing circuit to send a read request to a memory coupled to the PCIe device, the memory comprising a shared virtual memory. ### Claim 15 (depends on 10) The method of claim 10, further comprising, when the process specific information comprises a domain identifier, in response to a single invalidation request, invalidating a plurality of entries of a device translation lookaside buffer associated with the domain identifier, the plurality of entries associated with a plurality of process address space identifiers of a virtual machine having the domain identifier. ### Claim 16 A system comprising: at least one central processing unit (CPU), the at least one CPU to send an offload request to at least one accelerator, the at least one CPU comprising: a memory management unit (MMU) to translate a linear address to a physical address; and mask circuitry to mask one or more portions of a linear address and provide the masked linear address to the MMU; the at least one accelerator coupled to the CPU, the at least one accelerator to perform an operation in response to the offload request, the at least one accelerator comprising: a cache memory having a plurality of entries, each of the plurality of entries to store process specific information for a process; an input/output MMU (IOMMU) coupled between the at least one CPU and the at least one accelerator; and a memory coupled to the at least one CPU and the at least one accelerator, the at least one CPU and the at least one accelerator to interact with the memory according to a shared virtual memory (SVM) model, wherein: the at least one CPU is to send the offload request to the at least one accelerator, the offload request comprising an unmasked linear address, the unmasked linear address including metadata of a process; and the at least one accelerator is to communicate, to the at least one CPU, capability information to indicate that the at least one accelerator includes the cache memory to store the process specific information, and enable the cache memory in response to a configuration message from the at least one CPU. ### Claim 17 (depends on 16) The system of claim 16, wherein the at least one accelerator is to mask the one or more portions of the linear address and provide the masked linear address to the IOMMU to obtain a physical address. ### Claim 18 (depends on 16) The system of claim 16, wherein the process specific information comprises mask information for the process, wherein the at least one accelerator is to mask the one or more portions of the linear address using the mask information. ### Claim 19 (depends on 18) The system of claim 18, wherein the at least one accelerator further comprises a device translation lookaside buffer (DevTLB) having a plurality of entries each to store a virtual address-to-physical address translation received from the IOMMU, wherein in response to an invalidation message for a virtual machine having a first domain identifier, the accelerator is to invalidate entries of the DevTLB associated with the first domain identifier.