# US 12,222,855 B2 · Memory controller for scheduling commands based on response for receiving write command, storage device including the memory controller, and operating method of the memory controller and the storage device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,222,855 B2 - Document ID: US12222855B2 - Status: Granted - Kind: B2 - Application number: 18/148,149 - Filed: 2022-12-29 - Published: 2023-05-04 - Granted: 2025-02-11 - Earliest claimed: 2019-11-25 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Do Hun Kim; Ju Hyun Kim; Jin Yeong Kim - Web page: https://patentgrep.com/patent/US12222855B2 ## CPC - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)} - G06F 12/0804: with main memory updating (G06F12/0806 takes precedence) - G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems - G06F 13/1605: {based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36)} - G06F 13/1668: {Details of memory controller} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An electronic device includes a memory controller having an improved operation speed. The memory controller includes a processor configured to generate commands for accessing data stored in a main memory, a scheduling circuit configured to store the commands and output the commands according to a preset criterion, and a filtering circuit configured to store information on an address of the main memory corresponding to a write command among the commands, provide a pre-completion response for the write command to the scheduling circuit upon receiving the write command, and provide the write command to the main memory. ## Claims ### Claim 1 A memory controller comprising: a main memory configured to store data; a processor configured to generate commands for accessing the main memory; a scheduling circuit configured to receive the commands, re-order the commands based on each addresses of the main memory corresponding to the commands, and output a first command among the commands; and a filtering circuit configured to provide the first command to the main memory based on whether a first address corresponding to the first command is included in address information including an address corresponding to a command for which an operation completion response is not received from the main memory. ### Claim 2 (depends on 1) The memory controller of claim 1, wherein the filtering circuit provides a pre-completion response to the scheduling circuit after providing the first command to the main memory. ### Claim 3 (depends on 2) The memory controller of claim 2, wherein the scheduling circuit outputs a second command having same address as the first address among the commands in response to the pre-completion response. ### Claim 4 (depends on 3) The memory controller of claim 3, further comprising: a cache memory located between the scheduling circuit and the filtering circuit and configured to store the data that the processor accesses the main memory. ### Claim 5 (depends on 4) The memory controller of claim 4, wherein the cache memory provides data corresponding to the second command to the scheduling circuit before the filtering circuit receives a first operation completion response of the first command from the main memory. ### Claim 6 (depends on 3) The memory controller of claim 3, wherein the filtering circuit includes the first address in the address information after providing the first command to the main memory. ### Claim 7 (depends on 6) The memory controller of claim 6, wherein the filtering circuit removes the first address in the address information after receiving a first operation completion response of the first command from the main memory. ### Claim 8 (depends on 3) The memory controller of claim 3, wherein the filtering circuit holds the second command without outputting the second command to the main memory until a first operation completion response of the first command is received from the main memory. ### Claim 9 (depends on 1) The memory controller of claim 1, wherein the scheduling circuit re-orders a second command and a third command sequentially received from the processor among the commands, and outputs the third command prior to the second command. ### Claim 10 (depends on 9) The memory controller of claim 9, wherein the second command has an address same as the first address, and wherein the third command has an address different from the first address. ### Claim 11 (depends on 1) The memory controller of claim 1, wherein the scheduling circuit outputs a third command in response to a pre-completion response received from the filtering circuit before an operation corresponding to the first command is completed. ### Claim 12 (depends on 11) The memory controller of claim 11, wherein operations corresponding to the first and third commands are performed in parallel. ### Claim 13 (depends on 11) The memory controller of claim 11, wherein the scheduling circuit outputs the second command after outputting the third command. ### Claim 14 (depends on 13) The memory controller of claim 13, wherein the scheduling circuit receives data corresponding to the second command from a cache memory located between the scheduling circuit and the filtering circuit before the operations corresponding to the first and third commands are completed. ### Claim 15 A memory controller comprising: a main memory configured to store data; a processor configured to generate commands for accessing the main memory; a scheduling circuit configured to receive the commands, re-order the commands based on a result of comparing each addresses of the main memory corresponding to the commands, and output the commands; and a filtering circuit configured to store address information including an address corresponding to a command for which an operation corresponding to the command is not completed, and hold or provide the commands received from the scheduling circuit to the main memory based on the address information. ### Claim 16 (depends on 15) The memory controller of claim 15, wherein the address information is updated when the command is provided to the main memory or the operation corresponding to the command is completed. ### Claim 17 (depends on 16) The memory controller of claim 16, wherein the scheduling circuit re-orders a second command and a third command among a first command, the second command, and the third command sequentially received from the processor, and sequentially outputs the first command, the third command, and the second command. ### Claim 18 (depends on 17) The memory controller of claim 17, wherein the first command has an address of the main memory same as the second command, and wherein the third command has an address different from the first command. ### Claim 19 (depends on 17) The memory controller of claim 17, further comprising: a cache memory configured to cache data provided between the scheduling circuit and the filtering circuit. ### Claim 20 (depends on 19) The memory controller of claim 19, wherein, when data corresponding to the second command or the third command is stored in the cache memory, the cache memory provides the data corresponding to the second command or the third command before a first operation corresponding to the first command is completed. ### Claim 21 (depends on 20) The memory controller of claim 20, wherein the filtering circuit holds the second command without outputting the second command to the main memory until the first operation is completed. ### Claim 22 (depends on 21) The memory controller of claim 21, wherein the filtering circuit provides the third command to the main memory while the first operation is performed when the data corresponding to the third command is not stored in the cache memory.