# US 12,222,853 B2 · Method of sharing memory resource for memory cloud and memory resource sharing system using the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,222,853 B2 - Document ID: US12222853B2 - Status: Granted - Kind: B2 - Application number: 18/143,177 - Filed: 2023-05-04 - Published: 2024-03-14 - Granted: 2025-02-11 - Earliest claimed: 2022-05-04 - Assignees: Cosignon - Applicants: Cosignon - Inventors: Jang Ho Park - Web page: https://patentgrep.com/patent/US12222853B2 ## CPC - G06F 12/023: {Free address space management} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)} - G06F 2212/1024: Latency reduction - G06F 2212/1044: Space efficiency improvement - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7205: Cleaning, compaction, garbage collection, erase control - G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Provided is a memory resource sharing system including a first memory, a first memory subsystem configured to identify and distribute resources of the first memory and to control data transmission of the first memory, and a first processor unit including a first processor connected to the first memory subsystem, a second memory, a second memory subsystem configured to identify and distribute resources of the second memory and to control data transmission of the second memory, and a second processor unit including a second processor connected to the second memory subsystem, wherein the first memory subsystem and the second memory subsystem are communicatively connected to each other through a memory bus. ## Claims ### Claim 1 A memory resource sharing system comprising: a first memory; a first memory subsystem configured to identify and distribute resources of the first memory and to control data transmission of the first memory; a first processor unit comprising a first processor connected to the first memory subsystem; a second memory; a second memory subsystem configured to identify and distribute resources of the second memory and to control data transmission of the second memory; and a second processor unit comprising a second processor connected to the second memory subsystem, wherein the first processor unit communicates with the second processor unit via an Ethernet communication channel, and the first memory subsystem communicates with the second memory subsystem through a memory bus that is a data transmission channel separate from the Ethernet communication channel. ### Claim 2 (depends on 1) The memory resource sharing system of claim 1, wherein, when the first memory subsystem determines that a capacity of resources of the first memory is insufficient in response to a memory resource request of the first processor, the first memory subsystem is configured to transmit an access permission request message with respect to resources of the second memory to the second memory subsystem. ### Claim 3 (depends on 2) The memory resource sharing system of claim 2, wherein, when the second memory subsystem determines that the capacity of the resources of the second memory is sufficient in response to the access permission request message, the second memory subsystem is configured to transmit an access permission message with respect to the resources of the second memory to the first memory subsystem. ### Claim 4 (depends on 1) The memory resource sharing system of claim 1, wherein, when the first memory subsystem determines that data corresponding to a data read command does not exist in the first memory in response to the data read command of the first processor, the first memory subsystem is configured to transmit an access permission request message with respect to data of the second memory to the second memory subsystem. ### Claim 5 (depends on 4) The memory resource sharing system of claim 4, wherein, when the second memory subsystem determines that data corresponding to the data read command exists in the second memory in response to the access permission request message, the second memory subsystem is configured to transmit an access permission message with respect to the data of the second memory to the first memory subsystem. ### Claim 6 (depends on 1) The memory resource sharing system of claim 1, wherein, when the first memory subsystem determines that it is impossible to execute a data write command in the first memory in response to the data write command of the first processor, the first memory subsystem is configured to transmit an access permission request message with respect to the second memory to the second memory subsystem. ### Claim 7 (depends on 6) The memory resource sharing system of claim 6, wherein, when the second memory subsystem determines that it is possible to execute the data write command in the second memory in response to the access permission request message, the second memory subsystem is configured to execute the data write command in the second memory. ### Claim 8 (depends on 1) The memory resource sharing system claim 1, further comprising a first memory bridge integrated circuit (IC), the first memory bridge IC comprising a fifth memory and a first memory bridge subsystem configured to identify and distribute resources of the fifth memory and control data transmission of the fifth memory, wherein the first memory bridge subsystem is communicatively connected to the first memory subsystem and the second memory subsystem through the memory bus. ### Claim 9 (depends on 8) The memory resource sharing system claim 8, further comprising a second memory bridge IC, the second memory bridge IC comprising a sixth memory and a second memory bridge subsystem configured to identify and distribute resources of the sixth memory and control data transmission of the sixth memory, wherein the second memory bridge subsystem is communicatively connected to the first memory bridge subsystem through the memory bus. ### Claim 10 (depends on 8) The memory resource sharing system claim 8, further comprising a third memory; a third memory subsystem configured to identify and distribute resources of the third memory and control data transmission of the third memory; and a third processor unit comprising a third processor connected to a third memory subsystem, wherein the third memory subsystem is communicatively connected to the first memory bridge subsystem through the memory bus, and when the first memory subsystem and the third memory subsystem are not connected to each other through the memory bus, and when the first memory subsystem determines that a capacity of the resources of the first memory is insufficient in response to a memory resource request of the first processor, the first memory subsystem is configured to transmit an access permission request message with respect to resources of the third memory to the third memory subsystem through the first memory bridge subsystem. ### Claim 11 (depends on 1) The memory resource sharing system of claim 1, wherein the first memory subsystem is configured to transmit an access permission request message to the second memory subsystem without transferring data from the first memory through the first processor unit to the Ethernet communication channel.